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<
keesj >
when using trystate on the ice40 (open toolchain) do I need to use SB_IO blocks (I am trying to implement open drain coms)
12:14
<
q3k >
there's some support for inference of tristate in yosys but iirc it's fairly limited
12:14
<
q3k >
and i don't think anyone uses it seriously even in non-yosys flows
12:14
<
q3k >
so generally instantiating SB_IO and using that explicitly is the best way to go about it, regardless of the toolchain
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<
q3k >
*inference of tristate IO into SB_IOs
12:15
<
tnt >
if you want it done right, do it yourself.
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<
keesj >
DIY results in ERROR: cell type '$_TBUF_' is unsupported (instantiated as 'swim_$_TBUF__Y'). propably a worse outcome
12:27
<
keesj >
the nice thing is that I have already the usb core in there where I can copy from... good for confidence
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<
keesj >
and should I expect to be able to set a pin to 1'bz or shoud I rely more on the enable/disable of the IO block then?
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<
keesj >
e.g in open drain I kinda need to ther pull down to ground or high impedence mode
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<
q3k >
no, if you go with SB_IO it's all controlled by non-tristate signals
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<
q3k >
unless i misunderstood what you're saying
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tnt >
yup, wire D_OUT_0 to 1'b0 and then your control signal to OUTPUT_ENABLE.
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<
keesj >
I set D_OUT_0 to 1b'0 and assign io_enable to io_enable = cnt > 0 && current_data == 1'b0; (e.g. sending data and the data is 0)
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<
tnt >
you really don't need to wire D_IN_0 if you're not using it.
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<
keesj >
I hope in the furture to actually use it! but for now.. a logic analyzer will do
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<
promach3 >
For DDR3 memory, it seems that both `DQ` and `Command` signals are 90 degree out-of-phase with respect to `CK` ?
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<
keesj >
well. Command is read on the rising edge yes. dq (the address lines) can change every clock edge (e.g. dual data rate) and are read by syncing to a dqs signal.
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<
keesj >
It has been a while (and I never actually implemented ddr3), did use Arty-A7 to real time trace ddr command/state machine
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