16:32 <mindtree[m]> Hey folks - just wondering if anyone knows off hand if the DMAs are truly asynchronous not only with the CPU but with each other? E.g. I assume it is possible for one DMA buffer to be written over an SPI interface while another DMA buffer is simultaneously being written over I2C?

16:33 <mindtree[m]> Or another potential case - I assume it is also possible for one DMA buffer to be written over an SPI interface while the CPU synchronously writes to I2C, or UART at the same time?

16:35 <dirbaio[m]> I think it's 1 read/write per cycle per bus

16:35 <dirbaio[m]> so technically dma and cpu can't write both to an apb1 peripheral at the same time, for example

16:35 <dirbaio[m]> but unless you're writing 1 word per cycle, there's enough bus capacity and both accesses get interleaved so in practice it's as they were "at the same time"

16:36 <dirbaio[m]> * but unless you're writing 1 word per cycle, there's enough bus capacity and both accesses get interleaved so in practice it's as if they were "at the same time"

16:38 <mindtree[m]> Thanks dirbaio, I suspected something like this would be the case, makes sense

19:52 <sh3rm4n[m]> Hey I just wanted to ask, if someone can add me to the stm32-rs github group? Well at least if it does makes sense. I'm (sporadically) maintaining the stm32f3xx-hal for a while now and do not want to be left out 😛

19:52 <sh3rm4n[m]> I'm curious, does this even get me relevant benefits, if I'm concentrating my work mostly on this one repository? I'm fine not beeing part of the group, if it does not give me relevant benefits. . I'm just curious to know what your opinion is on this.

20:08 <therealprof[m]> adamgreig has been trying to make the groups more uniform. Pretty sure he'll add you when he's back. Not so sure about benefits, especially since you're already maintaining it. Probably just the warm fuzzy feeling to be a more integral part of the org. 😅

20:28 <adamgreig-m> sh3rm4n: absolutely, I think I even tried sending an invite before when I was updating the teams

20:28 <adamgreig-m> I've invited you now in any event, including to the stm32f3 team

20:28 <adamgreig-m> the only difference is that it gives you the 'Member' badge when you comment on things I guess :P you already had admin access to the f3xx-hal repo

21:02 <firefrommoonligh> Works on `l4x3`, and I've confirmed they exist in the user manual

21:03 <firefrommoonligh> Note that this only affects the NVIC interrupts, not the timers themselves

21:04 <firefrommoonligh> I can't check Rust docs due to it not being built for this variant

21:06 <dirbaio[m]> they're named `TIM1_BRK_TIM15` in the C headers, maybe try that?

21:06 <firefrommoonligh> Hah!

21:06 <firefrommoonligh> I bet that's it. I've seen similar things before

21:06 <dirbaio[m]> but they're named like that on l4x3 C headers too so idk 🤷‍♂️

21:07 <adamgreig-m> https://github.com/stm32-rs/stm32-rs-nightlies/blob/master/stm32l4/src/stm32l4x2/mod.rs#L252

21:08 <dirbaio[m]> yep, SVD inconsistency

21:08 <firefrommoonligh> Nailed it bros! You're both spot on

21:08 <firefrommoonligh> I'll save that GH for ref. you've shown me before, but I forgot

21:09 <firefrommoonligh> Also, the IntelliJ Rust plugin lets me introspect pac::Interrupt... I should have checked that first

21:09 <dirbaio[m]> so there are ghosts lurking in SVD interrupts too, fun

21:42 <firefrommoonligh> F3 uses odd names too. My guess is someone (agg?) manually cleaned up the `l4x3` ones

21:42 <firefrommoonligh> * F3 uses the longer names too. My guess is someone (agg?) manually cleaned up the `l4x3` ones

22:06 <dirbaio[m]> nope they're like that from ST

22:06 <firefrommoonligh> oh hmm

22:07 <firefrommoonligh> But you said they're like that on the l3x3 headers, but not that way in the PAC

22:07 <firefrommoonligh> * But you said they're like that on the l4x3 headers, but not that way in the PAC

22:08 <dirbaio[m]> yup! 🤷‍♂️

22:08 <dirbaio[m]> just the SVD is different, the headers are consisten

22:08 <dirbaio[m]> * yup! 🤷‍♂️

22:08 <dirbaio[m]> just the SVD is different, the headers are consistent

23:21 <firefrommoonligh> Gotcha; thank you