ELLIOTTCABLE changed the topic of #elliottcable to: #ELLIOTTCABLE — “do something cool, shove it into throats, everyone thinks it's crap, then it's all amazing.” “everything else is just details.”
<purr>
<Nuck> I love the feeling of blood on my dick
cheezburger5000 is now known as audy
<jvulc>
...
<purr>
<whitequark> plastic food is awesome.
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<ELLIOTTCABLE>
hi, all
<alexgordon>
sup ELLIOTTCABLE
<ELLIOTTCABLE>
hi, alexgordon
<ELLIOTTCABLE>
VHDL or Verilog? Go.
<joelteon>
verilog
<ELLIOTTCABLE>
VHDL is appearing to be more powerful and well-designed for the task
<ELLIOTTCABLE>
afaictsf
<alexgordon>
ELLIOTTCABLE: trying to work out how to give chocolat an HTTP api
<ELLIOTTCABLE>
wy
<alexgordon>
had this idea of making it run a localhost http server for all scripting needs
<alexgordon>
then you could script it in any language that supports http
<alexgordon>
but mainly also because running node *inside* the chocolat process (like we do now) is pretty unstable
<alexgordon>
if node crashes, chocolat crashes
<alexgordon>
and it's impossible to update node because they change their build system -_-
<jvulc>
Looks like I'm finally going to stop using IRCcloud.
<rf>
you can't just run it in a subprocess or whatever
<jvulc>
It was free while it lasted ...
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<rf>
have the 'scripting interface' be stdio
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<ELLIOTTCABLE>
what's an rf
<ELLIOTTCABLE>
had whitequark telling me that rf would be the bane of me, yesterday
<rf>
lol
<purr>
lol
<ELLIOTTCABLE>
and things to debug rf would cost me ten grand or more
<ELLIOTTCABLE>
and look, here rf is
<rf>
I used to be russfrank
<ELLIOTTCABLE>
no, you used to be electrical signals on-the-wire
<ELLIOTTCABLE>
now you are in the air and are my bane
ELLIOTTCABLE is now known as ec
<rf>
haha
<ec>
look i am your ban, elliptical curves
* ec
uses ‘cryptography.’ it's super effective!
<ec>
whitequark: when you have time, test the J-link against your Maple STM32 for me, okay?
<ec>
whitequark: either way, I'll probably order *both* their suggested one, and the J-link. I've heard of the J before, so I'm sure it's worth having, but I'd also like to have the one that they claim works, with their board and tooling.
<ec>
I was interested in the Black Magic, but you made a really good point, re: who wants to have to be debugging their debugger? >,>
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<ec>
so, I think it'd be cool to have a web-IDE for learning VHDL and FPGA programming in general. I wonder if I could farm out an array of FPGAs, and micro-charge people for “running” their code on them, over the web. Like, write on a pretty website, or send the code via an HTTP API from your editor; share it, simulate it for free, or run it on an FPGA for a
<ec>
couple cents. Simulate various peripherals? idfk.
<ec>
oh, alex left. this is now boring.
ec is now known as ELLIOTTCABLE
<ELLIOTTCABLE>
I want to know more about the placing-and-routing step of FPGA ‘preparation’
<ELLIOTTCABLE>
it sounds fairly different from, idk, linking in a compiler
<ELLIOTTCABLE>
linking is fairly one-dimensional, right? happens in a linear range of memory space.
<ELLIOTTCABLE>
but it sounds like placing-and-routing is like … multi-dismensional linking. which sounds Totes Neat™.
<ELLIOTTCABLE>
whitequark:
<ELLIOTTCABLE>
“Emulation, in the context of embedded microprocessor programs, typically refers to executing programs on special in-circuit emulation (ICE) hardware designed to 1) run exactly like the target machine and 2) provide visibility, access, and control of the target machine in powerful ways, with emulation timing exactly equal to target timing. Thus, the
<ELLIOTTCABLE>
essence of emulation is based on physical hardware that reproduces the microprocessor's gates while adding gates designed for debugging.”
<ELLIOTTCABLE>
Is that what you were talking about? 'cause that makes sense to me, now, actually
<ELLIOTTCABLE>
‘Emulation’ means debugging, because you're *emulating the timing*, in a debugging environment. Not emulating the code, like with programming.
<ELLIOTTCABLE>
we could do with a dose of timing-emulation debugging in software development, sometimes. >,>
<ELLIOTTCABLE>
avoid some eigenbugs.
<ELLIOTTCABLE>
actually, that'd make a really interesting project …
<ELLIOTTCABLE>
IC level *software debugging*. A chip designed to *exactly* emulate (run) some code, but with extra hooks *at the hardware level*, allowing for the debugger to dig into your code, without changing timing at the software-level …
<ELLIOTTCABLE>
how's that for a first FPGA project? Emulating (illegally? :x) x86, and then running your compiled code with perfect timing, and then writing an abstraction layer for gdb to hook into your code at *that* level, instead of on *top* of the chip? :D
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* vigs
waves
* ELLIOTTCABLE
pats vigs
<vil>
hi
<purr>
vil: hi!
* vil
pats purr
* purr
rr
<ELLIOTTCABLE>
I'm not actually, rem, here. though.
<ELLIOTTCABLE>
so, vigs, we shall meet again. 'ta.
<vigs>
ELLIOTTCABLE: okiedoke!
<vigs>
vil: hey I don't think we've me
<ELLIOTTCABLE>
me
<ELLIOTTCABLE>
you should me
<vil>
no we definitely havn't you
<vigs>
We should me
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<ELLIOTTCABLE>
fucking jvulc
<ELLIOTTCABLE>
no
<jvulc>
yes
<jvulc>
I'm switching my shits over, yah?
<jvulc>
Now that IRCcloud's busting everyone's ballsacks wanting money.
<jvulc>
I will forever be known as the IRC user formally known as jvulc.
<jvulc>
I'm going to reinvent myself.
<ELLIOTTCABLE>
jvulc: wat
<jvulc>
wat wat
<joelteon>
wot wot
<vigs>
wat wat wat wat
<vigs>
Somebody get Mackelmore
<ELLIOTTCABLE>
fuck that, Savant
<ELLIOTTCABLE>
♫ Vario by Savant
<ELLIOTTCABLE>
anybody know if purr still does that?
<vil>
♫ Never gonna give you up
<vil>
apparently not
<ELLIOTTCABLE>
ah
<ELLIOTTCABLE>
♪ Savant - Vario
<purr>
ELLIOTTCABLE is listening to “Wildstyle”, by Savant
<ELLIOTTCABLE>
problem is, album-name of a *more popular* song, is the same as the song-name I want.
<ELLIOTTCABLE>
hm.
<vil>
yeah
<ELLIOTTCABLE>
-song Rick Astley
<purr>
ELLIOTTCABLE: “Never Gonna Give You Up” by Rick Astley: <http://tinysong.com/HHyt>, “Get Funky [Robin Skouteris]” by Daft Punk feat. Pharell Williams & Neil Rodgers vs. Madonna vs. Justin Timberlake feat. Jay Z vs. Michael Jackson vs. Chic vs. Indeep vs. Rick Astley vs. KC & The Sunshine Band vs. Neneh Cherry vs. Isaac Hayes vs. Owl City & Carly Rae Jepsen vs. US3 vs. : <http://tinysong.com/1cMfm>, “Together Forever” by Rick Ast
<ELLIOTTCABLE>
wat
<ELLIOTTCABLE>
anyway. hi!
<vil>
hi ELLIOTTCABLE
<ELLIOTTCABLE>
I went to the trouble to log into purr's host for that.
<ELLIOTTCABLE>
But, I can't be arsed to do all the things I've been putting off “until next time I bother to get out my SSH keys”
<ELLIOTTCABLE>
like, making purr shut the FUCK UP with the quotings, a little bit
<vil>
I wish I could build ssh keys into my System repo
<vil>
but that is a Terrible Idea™
<vil>
in literally every way
<ELLIOTTCABLE>
wat why would you want to
<vil>
ELLIOTTCABLE: so that I can have them in place after wiping a computer mostly
<ELLIOTTCABLE>
lol.
<purr>
lol
<vil>
but that's one of the reasons it's a Bad Idea™
<ELLIOTTCABLE>
don't keep them on your computer in the first place, silly
<vil>
because then all computers would get the same one
<vil>
but
<vil>
I'm lazy tho
<vil>
each computer gets a different key, if I lose it I revoke that one
<vil>
and I have one on a jump drive I carry to connect from other systems if absolutely necessary
<vil>
where are yours?
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<ELLIOTTCABLE>
USB key, or other places I'll decline to reveal, variously
<ELLIOTTCABLE>
I'm very mildly paranoid about security-related stuff
<whitequark>
ELLIOTTCABLE: sigh, backlog
<whitequark>
ok. VHDL or Verilog? Verilog.
<ELLIOTTCABLE>
whyzdat
<whitequark>
it's the same thing, but VHDL will make you want choke yourself, because it was designed by the same crazies who did Ada
<whitequark>
extra verbose for no real reason
<ELLIOTTCABLE>
I created a GitHub repository for my apartment. >,>
<whitequark>
there are no free toolchains (PAR), and doing this is a Huge Fucking Task. hundreds of man-years or something.
<whitequark>
you're welcome to do it, of course
<ELLIOTTCABLE>
doing what is a huge fucking task?
<whitequark>
place and route.
<ELLIOTTCABLE>
mind is elsewhere, sorry
<whitequark>
the FPGA bitstream is even openly documented in most if not all cases!
<whitequark>
it's just a huge ball of almost impenetrable math requiring tons of background.
<whitequark>
just fyi.
<whitequark>
otherwise, webide... idk you could simulate with something like verilator, BUT
<whitequark>
I suggest you to use Xilinx ISE first and look at the complexity of even just the IDE itself
<whitequark>
not the parts they have, the parts you'd *want* to have.
<whitequark>
so, PAR is placing stuff in a two-dimensional matrix while satisfying tons of constraints
<whitequark>
it's as np-complete as it gets and it takes hours for even very simple processors on very powerful machines in a ridiculously optimized xilinx toolchain
* whitequark
shrugs
<purr>
¯\(º_o)/¯
* ELLIOTTCABLE
eyebrows
<ELLIOTTCABLE>
PAR takes hours?
<ELLIOTTCABLE>
wow.
<ELLIOTTCABLE>
this shit's all crazy. :D
<whitequark>
days sometimes
<whitequark>
so.
<whitequark>
in-circuit emulation
<whitequark>
it's a remnant of the past. any modern chip with JTAG is both the processor itself and its own emulator.
<whitequark>
in the past it was too complex to do, so they had different version, think debug vs release version of the chip
<whitequark>
now there's no need for it.
* ELLIOTTCABLE
nods
<ELLIOTTCABLE>
so why don't we debug the shit we compile to x86 with JTAG, then?
<whitequark>
first, x86 processors totally have JTAG
<whitequark>
it's just that most users don't want to use it because they don't want to connect crap to their motherboard, they don't want to buy debugger costing I don't even want to know much, and it's simply much more convenient to let the OS do arbitrage between debugger and debuggee.
<whitequark>
not even talking about how you'd need to standardize the debug interface (it's done for Cortexes, it was never done for x86, etc)
<whitequark>
(bbc thing) it's totally valid
<whitequark>
but a) it's only downlink (think how satellite internet works. downlink is satellite uplink is like dialup 56k)
<ELLIOTTCABLE>
are debuggers more expensive for different chips?
<whitequark>
b) line of sight, do you really want that? c) lights need to be on, do you really want that?
<whitequark>
well, it varies.
<ELLIOTTCABLE>
i.e. j-link can't be used on, say, an Intel chip on my motherboard?
<whitequark>
j-link cannot.
<whitequark>
it implements specifically cortex debug protocol
<ELLIOTTCABLE>
ah, k.
<ELLIOTTCABLE>
so cortex protocol runs on top of JTAG, higher-level thing.
<whitequark>
for various reasons doing partly with speed partly with vendor lock-in
<ELLIOTTCABLE>
and x86'll be using something else.
<whitequark>
JTAG is incredibly low-level. JTAG is basically SPI with very few additions on top.
<ELLIOTTCABLE>
mmm.
<whitequark>
the debugger cost also heavily depends on its *speed*.
<ELLIOTTCABLE>
is an x86 debugger more expensive, or is a *faster-processor*-debugger more expensive?
<ELLIOTTCABLE>
which axis caused the “I don't even want to know how expensive”
<ELLIOTTCABLE>
mm l
<ELLIOTTCABLE>
mm k*
<whitequark>
so if you want to get some data in realtime from a 10MHz chip, or from a 3GHz chip
<whitequark>
the latter will cost you a fortune, the former, well, a much smaller fortune
<whitequark>
also, if not for realtime data (this is called "tracing"), there's really not very much point in chip-level debug for something as huge and complex as x86
<whitequark>
it's significantly *easier* to debug an OS with a tiny debug stub for serial port linked in and attached to a fault handler or something
<whitequark>
and if it's not an OS, how are you even going to debug it at all? for example, most of the time you'll stop somewhere in totally not your code. also, virtual memory.
<whitequark>
so, there's just no need.
<purr>
<alexgordon> is that when the asians arrive?