ChanServ changed the topic of #nmigen to: nMigen hardware description language · code at https://github.com/nmigen · logs at https://freenode.irclog.whitequark.org/nmigen · IRC meetings each 1st & 3rd Monday at 1800 UTC · next meeting July 6th
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<_whitenotifier-b> [yosys] whitequark commented on issue #1: Crash on Windows with STATUS_BAD_STACK - https://git.io/JJIkz
<_whitenotifier-b> [YoWASP/yosys] whitequark pushed 1 commit to develop [+0/-0/±4] https://git.io/JJIIL
<_whitenotifier-b> [YoWASP/yosys] whitequark c14ba69 - Add yowasp-yosys-smtbmc binary.
<_whitenotifier-b> [YoWASP/nextpnr] whitequark pushed 1 commit to develop [+0/-0/±4] https://git.io/JJIIx
<_whitenotifier-b> [YoWASP/nextpnr] whitequark 41650dd - Update dependencies.
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<FL4SHK> time for me to make my SDRAM controller
<FL4SHK> I implemented temporal + spatial dithering for my VGA driver
<FL4SHK> it works!
<FL4SHK> at a higher resolution, it'd work even better
<FL4SHK> right now I can see the pixels slightly changing color
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<lkcl> cool!
<FL4SHK> Actually, I think making a scope first would make sense
<tpw_rules> is the dithering to save bit depth or something?
<FL4SHK> increases bit depth by 2
<FL4SHK> so I went from 12-bit VGA to 18-bit VGA
<FL4SHK> Building a DAC is probably more in line with what I want to do
<FL4SHK> I'd like 24-bit color
<lkcl> FL4SHK: there's a low-cost circuit for 18-bit DAC which i've used in the past. it's part of one of the olimex boards
<lkcl> it's basically a 74 series buffer IC followed by some resistors :)
<lkcl> kinda cool and minimalist
<lkcl> discrete DAC ASICs i've found are horrendously expensive
<FL4SHK> Like what?
<FL4SHK> I only need to build a couple
<tpw_rules> there's all kinds of cheap vga dacs
<FL4SHK> I need a non-SPI DAC
<lkcl> it was 4-5 years ago, and i was looking at a large volume
<FL4SHK> Yeah, that's not an issue for me
<lkcl> if you're only doing 1-2 then who cares :)
<FL4SHK> I'm only trying to build things for me
<lkcl> Chrontel CH7036
<FL4SHK> I want to be the one who designed my primary computer
<FL4SHK> If qemu-x86_64 can handle things, I can even be programming my FPGA board from my main computer
<lkcl> and as tpw_rules mentions, there's lots of RGBTTL to VGA converters out there
<lkcl> what kind of resolution are you looking at?
<tpw_rules> FL4SHK: what cpu will you be using to run qemu?
<FL4SHK> tpw_rules: it'd be a custom one
<FL4SHK> the main one of the machine
<tpw_rules> yeah, that's why i asked. what sort of power class?
<FL4SHK> I haven't written up an instruction set yet
<FL4SHK> well, I'd like to get it running at 500 MHz on my Arty A7 dev board
<FL4SHK> it's going to be really hard
<tpw_rules> do you have a way to expand the SDRAM?
<FL4SHK> the Arty A7 dev board has 256 MB of DDR3
<FL4SHK> I figured tat'd be enough for a time, at least
<FL4SHK> I also considered using multiple dev boards
<tpw_rules> i doubt you'll be able to synthesize a design using vivado through qemu before the heat death of the universe
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<tpw_rules> frankly i would just hope the open source toolchain is advanced enough by the time you get everything else working
<FL4SHK> is there one in development for Xilinx stuff?
<tpw_rules> yeah, for the series 7
<tpw_rules> but it's kind of in limbo i think
<FL4SHK> 256 MB of RAM is probably not enough
<FL4SHK> I don't think I'll competely abandon x86 machines until I get a dev board with enough RAM On it
<tpw_rules> do you have the 35T or the 100T arty?
<FL4SHK> the 100T
<FL4SHK> I wanted more LUTs :P
<FL4SHK> might even allow me to have two cores
<tpw_rules> yeah, xilinx recommends 3 gigs
<FL4SHK> I'll probably need to build a PCB
<FL4SHK> I'd ideally have like, 8 GB of RAM at least
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<FL4SHK> now time to use this font I built years ago
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<_whitenotifier-b> [YoWASP/yosys] whitequark pushed 1 commit to release [+0/-0/±4] https://git.io/JJIIL
<_whitenotifier-b> [YoWASP/yosys] whitequark c14ba69 - Add yowasp-yosys-smtbmc binary.
<_whitenotifier-b> [YoWASP/nextpnr] whitequark pushed 2 commits to release [+2/-2/±8] https://git.io/JJInh
<_whitenotifier-b> [YoWASP/nextpnr] whitequark efab2f8 - Export public functions to invoke the tools without a subprocess.
<_whitenotifier-b> [YoWASP/nextpnr] whitequark 41650dd - Update dependencies.
<_whitenotifier-b> [YoWASP/yosys] whitequark pushed 1 commit to develop [+1/-0/±0] https://git.io/JJIcB
<_whitenotifier-b> [YoWASP/yosys] whitequark 02c4d12 - Add an auto-updater.
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<_whitenotifier-b> [YoWASP/yosys] whitequark pushed 1 commit to develop [+1/-0/±0] https://git.io/JJIcz
<_whitenotifier-b> [YoWASP/yosys] whitequark 54fb95d - [skip ci] Add an auto-updater.
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<whitequark> neat
<tpw_rules> that seems like the opposite of what you want? i guess just for the gui
<tpw_rules> but you would still want cursors and stuff
<tpw_rules> also also, how are you gonna do the analog stuff for your scope?
<FL4SHK> tpw_rules: it's only a scope for the insides of the FPGA
<FL4SHK> i.e. I'm building a SignalTap
<FL4SHK> whitequark: how do I store a Record inside of a Memory?
<FL4SHK> without, uh, packing it myself
<FL4SHK> looks like I'll have to pack it myself
<FL4SHK> feature request: `shape` instead of `width` for `Memory`
<tpw_rules> FL4SHK: ah
<tpw_rules> but a signaltap with a display instead of just to a pc?
<FL4SHK> Yes
<FL4SHK> plus, I might expand the GPU later for a SNES ish game console.
<whitequark> FL4SHK: another thing to consider for the record split
<tpw_rules> i saw a thing on twitter recently of someone doing that
<FL4SHK> I have this monospaced font I drew a few years ago
<FL4SHK> going to use it for the scope
<tpw_rules> how big?
<FL4SHK> 8x16
<FL4SHK> It was originally for a GBA game I was working on
<tpw_rules> i find that too large. i like a nice 8x6
<tpw_rules> or 6x8
<FL4SHK> I've also got an 8x8 font I could use
<lkcl> FL4SHK: we created nmutil.noperator.cat (similar to python operator module) for pretty much exactly that purpose
<lkcl> a single line of code to pack records and unpack them.
<lkcl> you _can_ use nmigen.Cat() directly, however it packs Records as a sequence of bits, and the graphviz becomes more cumbersome to read, the larger the Record
<lkcl> https://git.libre-soc.org/?p=nmutil.git;a=blob;f=src/nmutil/nmoperator.py;hb=HEAD#l164
<lkcl> here's an example of where it's used:
<lkcl> https://git.libre-soc.org/?p=nmutil.git;a=blob;f=src/nmutil/singlepipe.py;hb=HEAD#l944
<lkcl> apologies for the use of higher-order functions, there.
<lkcl> the fundamental trick: it's possible to assign *to* a Cat(*list_of_something)
<lkcl> and therefore you can use that to pack *and unpack* a Record into a FIFO. or a Memory. or a Signal. or... anything.
<lkcl> minerva uses this same trick, somewhere, as well... where is it...
<lkcl> https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/minerva/units/loadstore.py;h=f3ca09d7af248f5d1826e93529b783dd9ffc39cf;hb=d652efe4157cfc39bc08685a4c7b968a1d9c236e#l166
<lkcl> that's a Record directly into a SyncFIFO - no "manual unpacking" - the Record is assigned directly to the Signal on the FIFO to get the data in, and the other way round to get the data out.
<whitequark> minerva doesn't actually assign to Cat()
<whitequark> right
<lkcl> yes, true. faulty memory, i thought it did.
<lkcl> i really like Cat(*some_list).eq(something) and vice-versa
<lkcl> it generates really tidy graphviz output as it centralises the signals being assigned.
<lkcl> a for-loop bit-level assignment gets... messy as anything (unreadable, unverifiable)
<whitequark> if the only verification you use is visual examination of netlists i have bad news
<lkcl> whitequark: of course not. i use it in combination with extensive unit tests, formal correctness proofs and more.
<lkcl> i remember our conversation from a couple years ago where you mentioned that graphviz does not tell the whole story
<lkcl> however i cannot count the number of times it saved me from making mistakes in using python-based expressions that expanded into absolutely massive ASTs
<lkcl> which yosys had absolutely no way of optimising out, due to the complexity
<lkcl> junior members of the team continue to make that mistake, and i can catch them (and teach them to catch them) by cursory examination of the graphviz output
<lkcl> (not as a substitute for *other* debugging and design techniques)
<tpw_rules> are there resources available yet on doing effective unit tests and formal verification with nmigen?
<whitequark> not really, as far as I know
<whitequark> the current simulator interface is quite bad for writing testbenches
<whitequark> the formal verification support is usable but definitely unpolished
<tpw_rules> hm. i think it's a skill i really need to start on
<lkcl> tpw_rules: yehh we had to piece it together. things like this
<lkcl> https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/alu/formal/proof_main_stage.py;hb=HEAD
<lkcl> where it was particularly valuable was this:
<lkcl> https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/logical/formal/proof_main_stage.py;hb=HEAD#l23
<lkcl> that's a simple_popcount. very obvious what it does (except performance is terrible)
<lkcl> but we use it to verify this, which is *not* obvious at all:
<lkcl> https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/logical/popcount.py;hb=HEAD
<lkcl> tpw_rules: we found that if it's a combinatorial block, Asserts and Assumes etc. can be thought of in a similar fashion to python and c++. sort-of.
<lkcl> michael nolan wrote this as a tutorial:
<lkcl> https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/logical/formal/proof_bpermd.py;hb=HEAD
<lkcl> and it verifies this rather obtuse implementation of the PowerISA bpermd instruction
<lkcl> https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/logical/bpermd.py;hb=HEAD
<whitequark> >Asserts and Assumes etc. can be thought of in a similar fashion to python and c++. sort-of.
<whitequark> this isn't just a coincidence! they really do have a similar execution model, intentionally so
<whitequark> the language guide specifies the exact behavior: https://nmigen.info/nmigen/latest/lang.html#active-and-inactive-assignments
<lkcl> cool! well, it worked - it got us understanding what's going on.
<whitequark> though the way i describe it in the language guide only works if you already understand the general idea; a tutorial (to be written) should describe it in much simpler terms first
<lkcl> interesting. i hadn't actually explicitly realised that i understood that nmigen worked in that "overwriting" fashion.
<lkcl> i worked it out by deducing the behaviour.
<lkcl> however i have seen others (junior team members) struggle to understand it
<lkcl> so it's definitely worthwhile emphasising in tutorials (and the language guide, like this)
<lkcl> whitequark: i like the way things refer back to each other in lang.html.
<lkcl> so when reading about "assignment order" it links back to "active and inactive" at a relevant context point.
<lkcl> it works well
<lkcl> ok - it works well for me :) i can see how someone new might still struggle with this, without a tutorial on the subject.
<lkcl> robert baruch's tutorial is superb as an introduction but doesn't cover subtle things like this
<whitequark> there absolutely needs to be a dedicated tutorial, the language guide is something i work on first because it's the foundation of the language. without an authoritative document defining what the behavior should be, there is no difference between a bug and a feature
<whitequark> (interestingly, it doesn't have to be very "formal", it just has to be clear and unambiguous. the C specification is what people often refer to as "formal" but it leaves a surprising number of details open to interpretation...)
<sorear> I think automated regression testing for resource usage would be a better idea than trying to vet every commit
<whitequark> either that or fixing it in the toolchain
<whitequark> resource usage is one of the things for which a linter is in fact appropriate
<sorear> what if I _want_ to make a flash ADC?
<whitequark> what do you mean?
<sorear> there are some real things that bear a strong resemblance to "someone forgot how loops work in EDSLs"
<whitequark> oh, sure
<whitequark> that's why it should be a linter (which you can disable), not a hard error
<whitequark> a lint*
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<_whitenotifier-b> [nmigen] alanvgreen synchronize pull request #420: Update license and copyright info - https://git.io/JJTYQ
<_whitenotifier-b> [nmigen] codecov[bot] edited a comment on pull request #420: Update license and copyright info - https://git.io/JJTYN
<_whitenotifier-b> [nmigen] alanvgreen reviewed pull request #420 commit - https://git.io/JJIzI
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<_whitenotifier-b> [nmigen] codecov[bot] edited a comment on pull request #420: Update license and copyright info - https://git.io/JJTYN
<_whitenotifier-b> [nmigen] codecov[bot] edited a comment on pull request #420: Update license and copyright info - https://git.io/JJTYN
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<_whitenotifier-b> [nmigen] codecov[bot] edited a comment on pull request #420: Update license and copyright info - https://git.io/JJTYN
<_whitenotifier-b> [nmigen] codecov[bot] edited a comment on pull request #420: Update license and copyright info - https://git.io/JJTYN
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<_whitenotifier-b> [nmigen] alanvgreen reviewed pull request #420 commit - https://git.io/JJI2I
<_whitenotifier-b> [nmigen] alanvgreen reviewed pull request #420 commit - https://git.io/JJI2I
<_whitenotifier-b> [nmigen] whitequark reviewed pull request #420 commit - https://git.io/JJI2x
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<_whitenotifier-b> [nmigen/nmigen] whitequark pushed 1 commit to master [+0/-0/±4] https://git.io/JJIaJ
<_whitenotifier-b> [nmigen/nmigen] whitequark 1fbd7f1 - docs: use sphinxcontrib-platformpicker.
<_whitenotifier-b> [nmigen] whitequark closed issue #416: Fix tab synchronization in installation guide - https://git.io/JJJEJ
<_whitenotifier-b> [nmigen/nmigen] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/JJIaw
<_whitenotifier-b> [nmigen/nmigen] whitequark 175c8a5 - docs: use working sphinxcontrib-platformpicker.
<_whitenotifier-b> [nmigen/nmigen] github-actions[bot] pushed 1 commit to gh-pages [+2/-0/±19] https://git.io/JJIah
<_whitenotifier-b> [nmigen/nmigen] whitequark 64ccd3b - Deploying to gh-pages from @ 175c8a596ef1adaa74961a47e48a0ed441c05809 🚀