<awygle>
it obviously needs a bunch of work to be production ready and the code is a learning-as-i-go mess, but i'm pleased that the idea turned out to be sound
<awygle>
including one triangle per bit, one draw call, etc
<awygle>
it's in opengl es 3.0 also so it should transition to webgl easily (or so lokathor assures me)
<whitequark>
uh, that needs webgl2
<whitequark>
not just webgl
<awygle>
o :( i don't know anything about the different versions honestly
<d1b2>
<edbordin> cr1901_modern so, imagine my surprise when I can make a bunch of symbiyosys test cases pass on windows. from what I gather looking at your old PR, the issues come when you try to kill a running job right?
<whitequark>
jfng: nice
<whitequark>
edbordin: fyi, I vetoed that PR back in the day, but I didn't have a solution offhand then
<whitequark>
if the PR is rebased on sby master I think I can write the Windows code that is required to get it merged
<d1b2>
<edbordin> whitequark yup, I got the backstory involving a bug in asyncio on windows that is apparently unresolved
<d1b2>
<edbordin> funnily enough I'm now hitting issues on darwin in CI that I didn't get locally
<d1b2>
<edbordin> oh I'm definitely happy to rebase that PR if it helps you
<whitequark>
edbordin: great, if you do that I'll volunteer to do the trick necessary to avoid shelling out
<cr1901_modern>
>I vetoed that PR back in the day
<cr1901_modern>
Is that why nobody offered any public feedback?
<cr1901_modern>
edbordin: There were two issues
<d1b2>
<edbordin> cr1901_modern seeing as you did most of the work so far are you happy for me to help out or would you rather keep running with it?
<cr1901_modern>
edbordin: By all means, feel free to help out.
<cr1901_modern>
The other issue is on Windows there isn't a working async ctrl+c handler
<cr1901_modern>
in python
<d1b2>
<edbordin> that...explains some things I've observed using python on windows
<d1b2>
<edbordin> namely, giant stack traces when pressing ctrl+c
<cr1901_modern>
Anyways for various reasons it became impossible for me to work on getting this merged and if I were to do it again at this point, I would restart from the beginning
<cr1901_modern>
"The Hard Way" is also a correct way to do this
<cr1901_modern>
Which isn't quite as difficult as I make it out to be, I just _really_ didn't want to do it
<d1b2>
<edbordin> well, given it is now approaching my bedtime I won't dive into anything right now
<d1b2>
<edbordin> but I seem to be torn between whitequark saying we can make it work and cr1901_modern saying we should start again 😛
<whitequark>
edbordin: i'm only talking about the taskkill part
<whitequark>
i can do the ctypes thing, it's not hard
<cr1901_modern>
I'm confused about the ctypes thing
<cr1901_modern>
if you go the async route, do we need ctypes?
<cr1901_modern>
I thought ctypes was only used if we do things "The Hard Way" in the linked GH comment.
<cr1901_modern>
whitequark: To be clear: _AFAIR_, the taskkill thing never appeared until I tried the async approach
<d1b2>
<edbordin> perhaps whitequark is proposing using ctypes to achieve the same effect as taskkill
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<whitequark>
exactly
<cr1901_modern>
Well, the bug report has a MCVE if you want to start w/ that
<d1b2>
<edbordin> I know this would never fly but it would be pretty easy to just pull this package in and call it day >_< https://pypi.org/project/psutil/
<d1b2>
<edbordin> (I can see the lack of pip infrastructure means it would in fact not be easy to "just" pull it in)
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<_whitenotifier-b>
[nmigen] whitequark commented on issue #441: PS7 block not initialized on series-7 Zynq targets - https://git.io/JJlUU
<_whitenotifier-b>
[nmigen/nmigen] whitequark pushed 1 commit to cxxsim [+0/-0/±1] https://git.io/JJlUZ
<Kekskruemel>
whitequark: thanks for fixing the bug!
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<d1b2>
<286Tech> Can I use initial statements in nmigen?
<TD-Linux>
just give your Signal() a default value
<awygle>
Signal(reset=1)
<awygle>
for example
<d1b2>
<286Tech> Yes, that's the reset value.
<d1b2>
<286Tech> But I mean initial in the formal verification sense.
<awygle>
oh sure
<awygle>
Initial
<d1b2>
<286Tech> For example, I want to do the initial assert bla Verilog equivalent in nmigen.
<awygle>
in the same module as Past, Stable, Rose, Fell, etc
<d1b2>
<286Tech> Yeah I found it, but that's not exactly what I mean.
<d1b2>
<286Tech> It's just 1 at the first cycle of model checking, and 0 otherwise.
<awygle>
you probably have to do it manually. if Initial() Assume(signal == value)
<d1b2>
<286Tech> Ah ok
<awygle>
(which i expect is a direct mapping to what Yosys supports)
<d1b2>
<286Tech> Let's see if that works 🙂
<awygle>
or well you said `initial assert` so itd be `if Initial(): Assert` not Assume but you could probably have figured that out lol
<d1b2>
<286Tech> Well like I said before, you can do initial assert bla, but I don't know if that's what will be generated with your suggestion. Time to find out 😄
<d1b2>
<286Tech> Ok, so nmigen uses yosys's $initstate system verilog task to generate statements equivalent to initial blocks from what I can tell at a first glance.
<d1b2>
<286Tech> And it seems to work, but I'll check it out in more depth tomorrow after I get some sleep 🙂
<d1b2>
<286Tech> Good night peeps!
<awygle>
night :)
<_whitenotifier-b>
[nmigen] programmerjake commented on issue #443: add API to get simulation time for debugging - https://git.io/JJliY