ChanServ changed the topic of #nmigen to: nMigen hardware description language · code at https://github.com/nmigen · logs at https://freenode.irclog.whitequark.org/nmigen · IRC meetings each 1st & 3rd Monday at 1800 UTC · next meeting July 20th
jock-tanner has joined #nmigen
cr1901_modern has quit [Quit: Leaving.]
Degi has quit [Ping timeout: 258 seconds]
Degi has joined #nmigen
cr1901_modern has joined #nmigen
electronic_eel has quit [Ping timeout: 256 seconds]
electronic_eel_ has joined #nmigen
jaseg has quit [Ping timeout: 256 seconds]
jaseg has joined #nmigen
jock-tanner has quit [Ping timeout: 272 seconds]
jock-tanner has joined #nmigen
electronic_eel_ has quit [Ping timeout: 258 seconds]
electronic_eel has joined #nmigen
PyroPeter_ has joined #nmigen
PyroPeter has quit [Ping timeout: 256 seconds]
PyroPeter_ is now known as PyroPeter
_whitelogger has joined #nmigen
lkcl_ has quit [Ping timeout: 264 seconds]
hitomi2504 has joined #nmigen
hitomi2504 has quit [Read error: Connection reset by peer]
jeanthom has joined #nmigen
hitomi2504 has joined #nmigen
chipmuenk has joined #nmigen
<_whitenotifier-b> [nmigen/nmigen] whitequark pushed 7 commits to cxxsim [+3/-0/±11] https://git.io/JJGah
<_whitenotifier-b> [nmigen/nmigen] whitequark 48dcb1a - _toolchain.cxx: new toolchain.
<_whitenotifier-b> [nmigen/nmigen] whitequark 2bc405e - wip
<_whitenotifier-b> [nmigen/nmigen] whitequark dcded49 - wip
<_whitenotifier-b> [nmigen/nmigen] ... and 4 more commits.
<_whitenotifier-b> [nmigen/nmigen] whitequark pushed 1 commit to cxxsim [+0/-0/±3] https://git.io/JJGVM
<_whitenotifier-b> [nmigen/nmigen] whitequark c029fa4 - wip
<_whitenotifier-b> [nmigen/nmigen] whitequark pushed 1 commit to yowasp [+0/-0/±1] https://git.io/JJGVd
<_whitenotifier-b> [nmigen/nmigen] whitequark 24c695d - CI: use WASM yosys instead of building our own.
<whitequark> Degi: do you think you could finish #73?
<whitequark> *sorry, nmigen-boards#73
<Degi> Oh yes
<whitequark> thanks
<_whitenotifier-b> [nmigen/nmigen] whitequark pushed 1 commit to yowasp [+0/-0/±1] https://git.io/JJGVj
<_whitenotifier-b> [nmigen/nmigen] whitequark b702fc5 - CI: use WASM yosys instead of building our own.
Asu has joined #nmigen
jeanthom has quit [Ping timeout: 265 seconds]
<_whitenotifier-b> [nmigen-soc] whitequark reviewed pull request #19 commit - https://git.io/JJGwm
<whitequark> jfng: reviewed, sorry for the delay
<_whitenotifier-b> [nmigen-boards] ECP5-PCIe opened pull request #81: Update SPI definitions to match the new terminology - https://git.io/JJGwV
<_whitenotifier-b> [nmigen-boards] whitequark closed pull request #81: Update SPI definitions to match the new terminology - https://git.io/JJGwV
<_whitenotifier-b> [nmigen/nmigen-boards] whitequark pushed 1 commit to master [+0/-0/±28] https://git.io/JJGwX
<_whitenotifier-b> [nmigen/nmigen-boards] ECP5-PCIe 19cf060 - [breaking-change] Update SPI pin names.
<_whitenotifier-b> [nmigen-boards] whitequark commented on pull request #73: Update SPI definition in interface.py to match new terminology - https://git.io/JJGwM
<_whitenotifier-b> [nmigen-boards] whitequark closed pull request #73: Update SPI definition in interface.py to match new terminology - https://git.io/JJTH4
<_whitenotifier-b> [nmigen/nmigen] whitequark deleted branch yowasp
<_whitenotifier-b> [nmigen] whitequark deleted branch yowasp - https://git.io/JJJOy
<_whitenotifier-b> [nmigen/nmigen] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/JJGrg
<_whitenotifier-b> [nmigen/nmigen] whitequark 5ccc212 - CI: use WASM yosys instead of building our own.
<_whitenotifier-b> [nmigen] whitequark closed issue #434: Use prebuilt yosys in CI - https://git.io/JJ3CE
<_whitenotifier-b> [nmigen/nmigen] github-actions[bot] pushed 1 commit to gh-pages [+0/-0/±13] https://git.io/JJGra
<_whitenotifier-b> [nmigen/nmigen] whitequark 171980d - Deploying to gh-pages from @ 5ccc2122ce42f5581957bbec998ff308d5b88b29 🚀
jeanthom has joined #nmigen
<whitequark> ... how do you actually program a quickfeather
<trabucayre> whitequark: it's a bit complex :)
<trabucayre> application (M4) structure is too much hardcoded
<whitequark> trabucayre: yeah I uh noticed
<whitequark> how did they manage to make hardware so profoundly unfun?!
<whitequark> I was really looking forward to using this device, too
<whitequark> jeanthom: is yosys#2271 blocking for you?
<trabucayre> I've spend some time to modify Makefile just to have a blink led without freertos & co
<whitequark> trabucayre: i would really appreciate it if you ended up compiling a repo with instructions and scripts that actually work
<trabucayre> script work. doc is WIP...
<whitequark> i'm not going to *ask* you to do this because it's free work for ql and they really ought to pay you (or some else) for this
<trabucayre> maybe yes ;-)
<jeanthom> whitequark, Yep, I have to use proc_mux and I suspect proc_mux to have some bugs :/
<trabucayre> it's joke. If someone may use ql easily with my script (and maybe some simplier makefile) it's most important
<whitequark> jeanthom: that seems rather unlikely re proc_mux, but regardless, I should be able to fix that fairly easily
<jeanthom> I'll re-do the tests once the always @* issue is fixed in Yosys
<_whitenotifier-b> [nmigen-soc] jfng reviewed pull request #19 commit - https://git.io/JJGPb
<_whitenotifier-b> [nmigen-soc] whitequark reviewed pull request #19 commit - https://git.io/JJGPh
<_whitenotifier-b> [nmigen-soc] whitequark closed pull request #19: periph: add a PeripheralInfo class for metadata. - https://git.io/JJvQM
<_whitenotifier-b> [nmigen/nmigen-soc] whitequark pushed 1 commit to master [+2/-0/±0] https://git.io/JJGXf
<_whitenotifier-b> [nmigen/nmigen-soc] jfng 1218e26 - periph: add a PeripheralInfo class for metadata.
<jfng> whitequark: wait, I didn't push the update for the NotImplementedError :D
<jfng> or maybe I could fix all getters in one commit
<whitequark> jfng: have you seen my comment?
<jfng> oh, it didn't refresh
<jfng> ok
<Lofty> whitequark: I was looking at the write_verilog -sv PR; are there any plans to use this for vendor targets that support it over normal Verilog mode?
<whitequark> Lofty: sure, why not
<whitequark> the main problem is that this will need to be detected by inspecting yosys version
<Lofty> Yeah, hmm
<Lofty> Or bundling an nmigen-yosys version known to have it
<whitequark> nope
<whitequark> can't require it, not available on all architectures
<whitequark> nmigen should at least work with every released yosys
<whitequark> er
<whitequark> with *some* released yosys
<Lofty> Okay, fair
<Lofty> Make an issue, and then possible wait until Yosys {0.10|1.0}?
<whitequark> sounds good
<daveshah> I am hoping that could be quite soon, as it would mean I could do the first release of nextpnr
<Lofty> Since the Yosys release cadence is, what, yearly?
<whitequark> daveshah: oh yeah I was wondering when that'll happen
<daveshah> I don't want to do a nextpnr release that requires non-release Yosys
<whitequark> right
<whitequark> on my side I'd really like to not have nMigen with known verilog or cxxrtl bugs which I have to work around for the next year
<jeanthom> whitequark, #2272 seems to work properly (actually a month or so ago I was doing s/always @*/always_comb/ until I went with proc_mux)
<_whitenotifier-b> [nmigen] Ravenslofty opened issue #437: Utilise `write_verilog -sv` for targets that support it - https://git.io/JJG1c
<jeanthom> now trying #2273
<jeanthom> yeah #2273 seems to work as well
jock-tanner has quit [Ping timeout: 256 seconds]
proteus-guy has joined #nmigen
DaKnig has quit [*.net *.split]
DaKnig has joined #nmigen
ianloic has quit [Ping timeout: 264 seconds]
ianloic has joined #nmigen
<zignig> the spice must flow.
pdp7 has quit [Excess Flood]
pdp7 has joined #nmigen
hitomi2504 has quit [Quit: Nettalk6 - www.ntalk.de]
<_whitenotifier-b> [nmigen-boards] jfng opened pull request #82: ecpix5: fix PMOD4 pins. - https://git.io/JJGA8
<_whitenotifier-b> [nmigen] jeanthom commented on issue #418: Simulation of Verilog output doesn't match nMigen simulation - https://git.io/JJGA6
<_whitenotifier-b> [nmigen] jeanthom closed issue #418: Simulation of Verilog output doesn't match nMigen simulation - https://git.io/JJGAi
<_whitenotifier-b> [nmigen-boards] jfng closed pull request #82: ecpix5: fix PMOD4 pins. - https://git.io/JJGA8
<_whitenotifier-b> [nmigen/nmigen-boards] jfng pushed 1 commit to master [+0/-0/±1] https://git.io/JJGxw
<_whitenotifier-b> [nmigen/nmigen-boards] jfng c379438 - ecpix5: fix PMOD4 pins.
jeanthom has quit [Ping timeout: 265 seconds]
<Ultrasauce> oh nice. axiom is a pretty interesting project
<d1b2> <נמר הגוקו> I hope this is the right place to ask - I have a question about reset signal. I integrate verilog module with my migen & LiteX design and the input signals for this module is clock and reset. how can I get these signals from my design? are they part of the CRG module?
<TD-Linux> in nmigen there is ClockSignal() and ResetSignal()
<d1b2> <נמר הגוקו> I dont want to create clock or reset signal
<d1b2> <נמר הגוקו> I would like to use the already exists system clock and reset signals
Asu has quit [Read error: Connection reset by peer]
Asu has joined #nmigen
<_whitenotifier-b> [nmigen] whitequark reopened issue #418: Simulation of Verilog output doesn't match nMigen simulation - https://git.io/JJGAi
<_whitenotifier-b> [nmigen] whitequark commented on issue #418: Simulation of Verilog output doesn't match nMigen simulation - https://git.io/JJGjV
Asuu has joined #nmigen
Asu has quit [Ping timeout: 240 seconds]
<trabucayre> whitequark: I've updated my repository with a script updated and filled the README
<whitequark> wonderful, thanks
<trabucayre> but after 2^n tries with n -> oo I not sure to have still clear ideas
<trabucayre> Reading docs and repo about CERN's white-rabbit must have burnt my last neuron too :)
<whitequark> whats your twitter again
<trabucayre> @GwenhaelG
<trabucayre> If you can try script and explanation, I know my script but it's sometime hard to be clear for other user (I'm alone in my head)
chipmuenk has quit [Ping timeout: 256 seconds]
chipmuenk has joined #nmigen
electronic_eel_ has joined #nmigen
electronic_eel has quit [Ping timeout: 264 seconds]
electronic_eel has joined #nmigen
electronic_eel_ has quit [Ping timeout: 272 seconds]
electronic_eel has quit [Ping timeout: 240 seconds]
electronic_eel has joined #nmigen
Yehowshua has joined #nmigen
chipmuenk has quit [Quit: chipmuenk]
jock-tanner has joined #nmigen
<Yehowshua> trabucayre : I'm searching for your QuickFeather repo? I'm not sure I caught the link?
Yehowshua has quit [Remote host closed the connection]
Yehowshua has joined #nmigen
<Yehowshua> key2: Another FOSS ECP5 FPGA... yay
Asuu has quit [Quit: Konversation terminated!]
DaKnig has quit [*.net *.split]
DaKnig has joined #nmigen
<awygle> Oh wow ktemkin you're on this week's embedded podcast? That's really cool!
<ktemkin> yep :)
<ktemkin> you can tell me if I’m terrible; as a rule I try not to watch my own talks / podcast appearances / etc =P