<Falteckz>
Completely burnt out and it's only Tuesday, but today is the day I write some darn nMigen! <3
<whitequark>
do be careful with that burnout
<Falteckz>
I appreciate that, thank you!
<Falteckz>
I've got simulation and gtkwave working in Windows in a snap, too easy. I've got boards working, just need the toolchain. What's the quickest way to get the TinyFPGA BX toolchain setup in Windows? With fusesoc I was doing everything through a docker container but I don't see a nice way to plug that into nmigen
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<_whitenotifier-b>
[YoWASP/yosys] whitequark pushed 1 commit to develop [+1/-0/±0] https://git.io/JJLQv
<_whitenotifier-b>
[YoWASP/yosys] whitequark a457fb4 - [skip ci] Add an auto-updater.
<Falteckz>
Yeah looks like it's being actively fixed, last activity an hour ago
<Falteckz>
Nice to see.
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<zignig>
Falteckz: what are you looking to do on your tinybx ?
<zignig>
I've been noodling with nmigen on mine for a while now.
<Falteckz>
I've just plugged a SiLabs USB/UART breakout in and am going to get UART working first - but after that I want to start working on an ALU, eventually getting my own CPU going. Either that or render some graphics to an OLED display at a high framerate, something that I've been unable to achieve previously with microcontrollers.
<Falteckz>
I've run a RISC-V core on it already, outside of nMigen, and I've played around with PWM, memory mapped IO and a few other concepts
<Falteckz>
I really want to put something together to be more useful than it's logical parts. Counters and basic peripherals are very cool to play with and learn from, but I would be unlikely to choose an FPGA in production just for those simple needs when something off the shelf for 30 cents will do it.
<Falteckz>
Oh! Also, DDS DAC! I want to play some music and see how good that sounds when compared to an 8bit resistor ladder
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<Falteckz>
What have you already done on yours, zignig ?
<zignig>
sounds cool , I have been working on a similar thing.
<zignig>
I have got @whitequarks boneless processor going as a SOC, with timer , CRC , serial ports.
<Falteckz>
What is meant by boneless?
<Falteckz>
I've designed a couple processors in Logisim and Digital https://github.com/hneemann/Digital and would love to move some of those to gateware
<zignig>
nice 16 bit processor , that is really flat with no crazyness in the instruction set.
<Falteckz>
That project is worth it's wait in gold just for the assembler in itself
<Falteckz>
I've written too many assemblers and all of them were an awful mess
<whitequark>
hah!
<Falteckz>
s/wait/weight/
<Falteckz>
Though it's Python - so maybe I don't correct that :P
<whitequark>
haaah
<whitequark>
it's not too slow
<whitequark>
one of the tests goes through all 65536 encodings
<Falteckz>
My last assembler was asyncio, so I've no leg to stand on with this accusation
<zignig>
Falteckz: and it in python , so you wrap it in classes and python structures. and build up constructs.
<zignig>
I have been bashing at some libs and a bootloader for way to long.
<Falteckz>
Solved jump labels that hadn't been discovered yet with cheeky yields. Saved doing multiple passes but I do not think the extra complexity was worth it
<zignig>
RL keeps getting in the way.
<Falteckz>
RL?
<zignig>
real life (TM)
<Falteckz>
Gotcha.
<Falteckz>
I thought you meant Rocket League which would have been fitting because I'm coding on nMigen while listening to the soundtrack
<zignig>
hehe
<_whitenotifier-b>
[nmigen/nmigen] whitequark pushed 3 commits to master [+0/-0/±4] https://git.io/JJLQa
<Falteckz>
Well okay I guess I'll use this kindly supplied stdlib and do nothing hahaha
<zignig>
stand on the shoulders of giants ?
<Falteckz>
I am absolutely all about that to be honest
<Falteckz>
Devoid of humour though, I stand on the shoulders of giants in my hobbies and reinvent the wheel in my professional life and I would really prefer roles were reversed
<zignig>
indeed, I know exactly what you mean.
<Falteckz>
If reinventing the wheel wasn't fun sometimes we wouldn't have Blinky, Hell World or Todo apps :D
<Falteckz>
s/Hell/Hello/
<Falteckz>
2020 Typo
<zignig>
I like Hell world better.
<zignig>
i'm in au , so all we need is war and pestilance... it's only july...
<tpw_rules>
didnt you have those already
<Falteckz>
I'm going to grok "au" as Australian
<Falteckz>
tpw_rules: How do you think they got there :D
<zignig>
tpw_rules: just fire and drought and pandemic.
<_whitenotifier-b>
[nmigen/nmigen-boards] whitequark pushed 1 commit to master [+0/-0/±1] https://git.io/JJLQQ
<_whitenotifier-b>
[nmigen/nmigen] github-actions[bot] pushed 1 commit to gh-pages [+0/-0/±13] https://git.io/JJL7o
<_whitenotifier-b>
[nmigen/nmigen] whitequark 781246c - Deploying to gh-pages from @ cee43f0de14020e91c047808f0ea092d92841c76 🚀
<awygle>
whitequark: what is the error message for "This is neither a Shape nor a correctly-typed tuple"? i started by saying "not a shape or a 2-tuple" but that's inaccurate since you can't compare with ("egg", "mcmuffin") obviously
<awygle>
"Shapes may be compared with other Shapes and (int, bool) tuples, not {!r}" maybe?
<awygle>
also i guess i should add a test for rejected comparisons huh...
<Falteckz>
I presume that Memory.data doesn't need to be updated on clock edge, and can be combinatorial?
<Falteckz>
Provided that what it is attached to, is synchronous
<zignig>
Falteckz: on ice40 I think it needs a cycle to load.
<Falteckz>
My thought is that this should be fine:
<Falteckz>
On the upside, it's consistently garbage
<d1b2>
<edbordin> at least the garbage is probably made of the characters you wanted haha
<Falteckz>
Haha yes! That too!
<Falteckz>
I wonder if that combinatorial thing is actually a problem, maybe the bits are not updating fast enough - I wouldn't think so though. It should have raised a timing error
<zignig>
what speed are you failing at ? 115200 works fine for me.
<zignig>
it also may be your serial converter, I assume that you are just using TX/RX on a usb<->serial tranceiver.
<Falteckz>
115200 works fine if I'm shifting the characters in 10/second
<Falteckz>
But when I shift the characters in as fast as possible it comes out as garbage
<Falteckz>
I'm trusting that `tx.rdy` is reliable, maybe it isn't
<Falteckz>
It's weird that it's in a START state when the shift register is empty
<Falteckz>
I would expect the state machine to wait for data to be present and then do START, BITS, STOP
<zignig>
could be an interlock at your loopback.
<zignig>
perhaps 2 fifos , to buffer it up before you get to the loopback.
<zignig>
let me have a look for an example.
<Falteckz>
There is no loopback
<Falteckz>
I've "Hello World" in ROM which I print
<zignig>
so out only.
<Falteckz>
It works fine at a slow clock rate (baud rate still 115200)
<Falteckz>
Yes, out only
<zignig>
and it BORKS at higher than that.
<Falteckz>
It BORKS at theoretical maximum/2
<Falteckz>
I'm looking at the AsyncSerialTX and I don't actually see logic for start and stop, the signals are set (and I don't know if they are sent correctly) but I don't see them used anywhere either
<zignig>
could be the read delay on the Memory.
<Falteckz>
The data that goes into the UART shift register is valid
<Falteckz>
In my screenshot, the "e" in data[7:0] goes to shreg__data[7:0] as 0x65
<Falteckz>
Have you tested nmigen-stdio:serial to it's maximum effort?
<Falteckz>
The implementation is so easy to understand in nMigen, I really appreciate how much cleaner it is
<zignig>
I have but only to 115200.
<zignig>
and it has significantly less footguns than verilog.
<Falteckz>
Did you saturate the bus at 115200?
<Falteckz>
I assume that's 11,520 characters / second saturated
<zignig>
didn't try , it was just a console for my boneless.
<_whitenotifier-b>
[nmigen-soc] Fatsie commented on pull request #21: [WIP]wishbone.Connector class - https://git.io/JJtqS
<_whitenotifier-b>
[nmigen-soc] Fatsie edited a comment on pull request #21: [WIP]wishbone.Connector class - https://git.io/JJtqS
<_whitenotifier-b>
[nmigen-soc] Fatsie commented on issue #18: Wishbone access from initiator bus with data_width smaller than the one of the subordinate bus. - https://git.io/JJtmL