marcan changed the topic of #asahi to: Asahi Linux: porting Linux to Apple Silicon macs | General project discussion | GitHub: https://alx.sh/g | Wiki: https://alx.sh/w | Topics: #asahi-dev #asahi-re #asahi-gpu #asahi-offtopic | Keep things on topic | Logs: https://alx.sh/l/asahi
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<marcan>
just a bit of commentary related to reverse engineering and copyright. *please* do due diligence before throwing stuff in a disassembler to make sure it's actually needed, and *please* do not just take code from other people who may have done the same
<marcan>
everyone sucks at this
<marcan>
e.g. pongoOS ripped off the USB driver from KTRW without attribution and replacing the license wholesale, which is an obvious copyright violation
<marcan>
but the KTRW guy wrote that original driver by reverse engineering the boot ROM code, because he somehow couldn't figure out that that USB IP core is just the same DesignWare thing that is used in the Raspberry Pi and a ton of other places?!
<marcan>
so yeah, that is clearly unnecessary exposure and I will be writing my own USB driver or importing it from some other non-iThing project that didn't involve reverse engineering and has a clearer licensing trail
<marcan>
but that's just an example of the kind of problems you will find with existing code that comes from the iDevice reverse engineering communities
<marcan>
please be careful with that kind of stuff, and don't do the same thing
<marcan>
(and a reminder about our copyright/RE policy at https://alx.sh/re for those who haven't read it yet)
<davidrysk[m]>
unfortunately I am not surprised by this
<davidrysk[m]>
if this is the dwc3 core, there are stacks in Linux, FreeBSD, and probably elsewhere.
<Necrosporus>
So does mini work on M1 yet?
<Necrosporus>
I have seen stream announce but I didn't watch whole six hours
<davidrysk[m]>
if it's the dwc_otg core, well, raspberry pi and android use a core from synopsys that has some weird license text but appears permissive
<Necrosporus>
Hm, probably not or it would be announced
<davidrysk[m]>
Necrosporus: what do you mean by "work"?
<Necrosporus>
Boots and shows some messages on UART?
<Necrosporus>
Or better boots and can load the kernel
<Necrosporus>
Which in turn can show some messages on UART
<rwhitby>
Necrosporus: boots, chain loads itself, kills watchdog, read/writes mem, etc all working
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<Necrosporus>
Interesting. What if you tell it to load a kernel binary?
<davidrysk[m]>
Necrosporus: marcan spent a lot of time working on device tree handling
<davidrysk[m]>
re apfs: apparently apfs has additional fields to make it easy to locate the boot object without having to parse/mount the standard filesystem structures. I wish we had the Apple Silicon version of the APFS documentation; Apple drags their feet on releasing it
<marcan>
you could just writemem(somewhere, linux) and call(somewhere, devtree) and that should boot linux, for "well it's missing drivers so it won't actually boot" values of booting linux
<marcan>
but I want USB support first because loading linux over serial is going to be painful
<enick_226>
I remember booting kernels using XMODEM on UART. It was awful.
* rwhitby
now has a glasgow rev C2 \o/
<maximus64>
my still estimate ship on May 31 :(
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<Necrosporus>
enick_226, I did that too, I have loaded openwrt kernel and rootfs (as initramfs) via UART and then from openwrt was able to backup the original firmware and flash the new one
<rwhitby>
I bought mine locally from greg davill (who I had the pleasure of meeting in person today)
<enick_226>
it’s a great way to spend time watching paint dry
<rwhitby>
maximus64: my campaign order has the same ship date as yours
<maximus64>
that awesome :)
<Necrosporus>
What is default/max serial speed of M1 UART?
<davidrysk[m]>
marcan: do we have any idea of how complex accessing the internal NAND will be?
<maximus64>
115200 is the default max is 1.5M
<davidrysk[m]>
1.5M wouldn't be TOO unbearable
<Necrosporus>
then if kernel binary is 7M, then it should load in 10 seconds
<Necrosporus>
Or wait, not quite...
<davidrysk[m]>
still, gonna need USB sooner rather than later
<davidrysk[m]>
though USBC is more useful than FL1100, but the latter might be simpler
<Necrosporus>
150 kilobytes per second, then 7 seconds per megabyte and 50 seconds for 7 megabytes
<maximus64>
I think you can strip kernel down to less than 1MB
<Necrosporus>
But with USB link being fast, it might be possible to upload whole kernel and rootfs to RAM every boot and to get a shell access with all the tools
<maximus64>
need to figure out the interrupt before we can even boot that far =)
<Necrosporus>
By USB did you mean mini's USB driver or kernel driver?
<Necrosporus>
Though for developers without special debug cable to be able to work, both are required
<marcan>
davidrysk[m]: we do not yet, but AIUI it should be handled by a separate controller
<marcan>
Necrosporus: mini's USB driver
<marcan>
and once I have that developers will be able to hack on mini without any special cables
<marcan>
there should already be a kernel driver for it
<marcan>
though I will probaby port over some minimal debug print support
<davidrysk[m]>
marcan: I don’t believe upstream Linux has support for the dwc otg core. It does have support for the dwc host mode cores
<davidrysk[m]>
(And the host mode driver might be fine for the otg core in host mode. Haven’t dug deep enough)
<marcan>
davidrysk[m]: drivers/usb/dwc2/gadget.c
<rjeli>
android all dwc otg
<Necrosporus>
Do any other devices have USB gadget mode with ttyACM device which provides access to unix-like shell when connected without UART?
<marcan>
it's not hard at all to find documentation for that core
<marcan>
(you just need to look for any of the million chips that include it, and find one with a good TRM)
<maximus64>
should be very easy to tell if it dwc usb controller. since all synopsys have magic register that store the IP core name + rev. I think in the driver it also check for the magic when probe
<maximus64>
USB might be power down on bootup. We might need to figure out how to power up / bring it out of reset
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<dhewg>
sounds like a job for uart proxy
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<Necrosporus>
maximus64, but in this case PD commands are sent to enable UART, so some chip should be powered up
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<yorick>
marcan: what kind of screen are you running, 32 inch?
<yorick>
(on the streams)
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<rwhitby>
Necrosporus: PD chip is completely separate from USB block on the M1, and is usually independently powered
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<marcan>
yorick: iMac retina 5K 27"
<yorick>
neat, thanks!
<marcan>
but at 4K because 5K needs another 8hr stream from me to figure out ( :-) )
<yorick>
stream quality is 1080p, no?
<marcan>
I run at 1.5x hidpi mode and then for the stream mirror-scale down to 1080p into an HDMI capture card
<marcan>
yeah
<j`ey>
the text is hard enough to read as is :P
<yorick>
why not do OBS with a screen capture?
<marcan>
basically you get 1.5/2 scaling vs what would be 1080p-looking for me
<marcan>
so it's a bit smaller than normal for 1080p, but no unreadably small
<marcan>
I do assume people are watching in 1080p
<marcan>
at 720p, forget about it
<marcan>
the weird halo/sharpening is my capture card, that's.... let's call it a 4hr stream to figure out and fix in these chinese capture cards :p
<yorick>
I have difficulty reading the code on a 1440p 27" screen, the terminals are fine
<j`ey>
I dont have a way to hook up my new mac to any external screen, and my old one can get a little cranky at watching 1080p for ages
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<j`ey>
yorick: ok, I feel a bit better that it isnt just me :)
<jix>
I didn't have any trouble reading it on a 24" 1080p monitor that's a bit farther away than my main monitor... but judging from how people usually comment on my font sizes, I don't get a vote here :)
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<clayfreeman>
marcan: did you ever figure out where the 0x200000000 is coming from for the wdt address?
<marcan>
yeah, I'm not resolving devicetree memory regions properly
<marcan>
need to write or find some code to do that (I'm sure I'm not the first one to do this on top of libfdt or a lookalike)
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<clayfreeman>
seems as though the registers are coming after the physical memory region; OR'ing the wdt register address with mem_size_actual seems to get you there
<marcan>
that's not how it works
<marcan>
at all
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<marcan>
you have to recursively go up the range blocks in the devicetree and apply those as translation functions
<marcan>
mem_size_actual has nothing whatsoever to do with it, that's just a coincidence
<j`ey>
clayfreeman: look at the arm-mmio section, higher up
<marcan>
what I'm wondering right now is how I want to implement that, because I can't recurse upwards through the tree given the current adt implementation, so I'll need a more self-contained lookup regs function that takes a path :)
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<yrlf>
@marcan: so IIRC you do a linear scan to find the target node anyway, right? would it be possible to make a get function that "collects" the range information while looking for the node?
<yrlf>
that way you don't have to do a second scan to get the range info. I don't have any experience with fdts other than watching your last work stream, so that's just a quick guess I had of what could maybe work
<clayfreeman>
is the devtree reference available anywhere in the asahi docs?
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<marcan>
yrlf: yeah, I'm thinking a variant of that that returns a node path that can then be crawled to resolver reg properties
<marcan>
clayfreeman: it is not, but the format is quite trivial, it should be fairly obvious from the two structures and the source
<marcan>
Shiz has a parser in Python too
<marcan>
it's just a trivial linear smash of everything
<marcan>
fee free to write a wiki page :)
<marcan>
*resolve reg properties
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<clover[m]>
will M1 be able to emulate x86 ala rosetta with asahi?
<j`ey>
clover[m]: you can do that with qemu
<davidrysk[m]>
yeah, though rosetta 2 uses ahead-of-time static recompilation and only falls back to interpreting / dynarec when needed
<davidrysk[m]>
I don't think there's anything FOSS that can do this efficiently
<j`ey>
my point was that it's not really in the remit of asahi!
<j`ey>
(apart from the TSO bit..)
<davidrysk[m]>
Yep, it's not :)
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<clover[m]>
ok, i was under the impression that what made rosetta work was hardware-related, and if that bit could be carried over into linux for a FOSS equivalent software to take advantage of
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<j`ey>
yeah, that's the bit that changes to total store order memory model
<j`ey>
but that will be about modifying qemu to use that, if possible
<j`ey>
someone could probably look at doing that now, since qemu runs on macOS
<clover[m]>
interesting!
<davidrysk[m]>
clover: the major thing that makes Rosetta work as well as it does is ahead-of-time recompilation.
<davidrysk[m]>
The TSO bit helps, but ahead-of-time helps more.
<davidrysk[m]>
I'm not aware of very many FOSS implementations of AOT recompilation. The RPCS3 emulator uses it for Cell SPU and PPU code; mcsema can do it but it's more geared towards reverse-engineering and not optimized for performance; there's also https://github.com/MerryMage/dynarmic but it's for the other way around (ARM on x86)
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<marcan>
it probably makes more sense to just add caching to qemu or something like that
<enick_226>
hi Mary
<clayfreeman>
I think I figured out how to calculate wdt's base address using #address-cells, #size-cells, & ranges - this is my first time ever dealing with device trees
<rjeli>
ik uart over dwc is pretty high priority, but it’s always nice to have a uart of last resort
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<awordnot>
davidrysk[m]: I'm working on a new FOSS high performance dynamic recompiler for linux userspace binaries, but it's still in very early stages (and the aarch64 backend hasn't been started yet :P)
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<davidrysk[m]>
awordnot: hmmm :)
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<jn__>
awordnot: are you aware of the research paper from the Elbrus/lintel people? i found it interesting
<awordnot>
jn__: I don't believe I've seen that one (though I have seen papers from Loongson and HQEMU on the same topic)
<jn__>
"Background Optimization in Full System Binary Translation" by Sokolov and Ermolovich is specifically what i'm thinking of
<jn__>
yep this one
<awordnot>
cool, I'll give it a read
<davidrysk[m]>
awordnot: are you familiar with asmjit? A bunch of software takes advantage of it to simplify the complexity of the internal backend
<jn__>
short, but i found the multiple optimization levels interesting
<davidrysk[m]>
It's not a dynamic recompiler as much as a library to make it easier to write a dynamic recompiler... MAME takes some advantage of it
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<awordnot>
davidrysk[m]: I have not seen this before - is it essentially just a macro assembler library?
<awordnot>
for my first backend targeting ppc64le I wrote the assembler and codegen from scratch and it wasn't that bad
<davidrysk[m]>
one of its features is just a macro assembler library, but it also has higher level features including register allocation
<davidrysk[m]>
it only has x86 (32/64) and aarch64 backends at this time
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<awordnot>
interesting. For ppc64le I'm getting away with basically no register allocator since I just map x86_64's few registers statically to some of ppc64le's
<awordnot>
and the rest I just "allocate" sequentially for scratch operations
<davidrysk[m]>
yeah. MAME's use of asmjit is only for the macro assembler library -- it does its own register allocation (which is a bit less than ideal because the MAME intermediate language has more registers than typical Intel machines)
<davidrysk[m]>
the intermediate language was designed when both PPC and x86 were common and it wasn't clear that Apple would dump PPC / PPC would become less relevant
<davidrysk[m]>
of course, now with ARM/aarch64 that will probably end up being an advantage
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<awordnot>
heh, interesting
<awordnot>
and yeah, targeting register-starved ISAs would make an allocator like this really useful
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<rwhitby>
rjeli: ideally it would have headers for A6/A7/B6/B7 and SBU1/SBU2.
<rwhitby>
rjeli: (and not have A6/A7/B6/B7 tied together, as they can be used separately in this scenario)
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<rwhitby>
rjeli: and for future expansion, have points for all the high speed lanes as well, as we think that perhaps those can be used for pinsets, but have not been able to test that yet