marcan changed the topic of #asahi to: Asahi Linux: porting Linux to Apple Silicon macs | General project discussion | GitHub: https://alx.sh/g | Wiki: https://alx.sh/w | Topics: #asahi-dev #asahi-re #asahi-gpu #asahi-offtopic | Keep things on topic | Logs: https://alx.sh/l/asahi
<marcan>
arnd: going to put together v3, but I just realized that your section of device-io.rst somewhat overlaps with, and partially contradicts, memory-barriers.txt
<marcan>
in particular, the latter says the _relaxed versions do *not* guarantee ordering with spinlocks
<marcan>
maz: re the AIC ordering, since the IPI ack is an MMIO *write*, not a *read*, and writel() orders before the write, not after, at the very least it seems I'd need a dma_wmb() after it, before the atomic op
<marcan>
(and in that case I can get away with the relaxed; the ordering before it is guaranteed by the readl() for the main AIC reason register)
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<marcan>
also, this commit is a good read: 22ec71615
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<arnd>
marcan: ok, sorry about my mistake. memory-barriers.txt is correct here. I had changed the writel() description to clarify that it is not ordered against spinlocks after cross-checking, but forgot to update the writel_relaxed() description
<arnd>
I think the correct explanation would be that both readl() and readl_relaxed() are fully ordered against spinlocks, while writel() and writel_relaxed() can be posted (depending on the device and mapping flags), which results in the store completion not being ordered against locking at all
<maz>
marcan: ah, fair point about writel.
<maz>
marcan: btw, I think the patch that moves all the ICC_* stuff into sysreg.h breaks 32bit builds (the GIC driver ls shared between the two architectures). Consider only moving the ICH_* definition instead.
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<kettenis>
marcan: ah good I couldn't find that text
<maz>
interestingly, there is no way to discover whether two blocks are in the *same* IS shareability domain.
<maz>
so you could have all the CPUs in one IS domain, the interrupt controller and the IOMMU in another IS domain, and you'd still have to order things at the OS level... :-/
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<marcan>
maz: already switched to only the required register in my local branch (or do you want all of ICH_*?)
<marcan>
I'll test the 32bit build anyway to make sure
<maz>
marcan: either way is fine by me, I'll leave it up to you.
<marcan>
I'll do all of it then, seems cleaner. I'll make sure 32bit still builds.
<maz>
cool.
<marcan>
glad I found that commit though, that finally explains the dmb vs dsb story
<marcan>
i.e. that it was a *change* in the spec
<marcan>
which obsoletes the older thinking that dsb is needed
<marcan>
so I'll buy that dmb is enough :-)
<marcan>
might still play around with making a little litmus test framework for m1n1 though, because this won't be the first ordering question we have, and with Apple's proprietary sysreg stuff there are unanswered questions anyway
<marcan>
(plus I might find more CPU bugs... hopefully not of the security variety this time)
<marcan>
watched a couple of Will's talks earlier too, those were a good source of info too (though now obsolete with the dmb story)
<kettenis>
I'm currently chasing an issue with crashing userland binaries that seems to be related to TLB flushing
<kettenis>
probably an OpenBSD bug revealed by th Apple cores doing more speculation
<maz>
kettenis: are you using ASIDs? or just global TLBs like FreeBSD?
<kettenis>
using ASIDs
<kettenis>
more or less the same way as Linux does, reserving two ASIDs per process to hide the kernel mappings
<kettenis>
but unlike Linux I flush the ASIDs when the process exits
<kettenis>
might very well be a case where I'm not following the right "break then make" procedure
<maz>
kettenis: I guess you have a strong guarantee that once you marked this ASID as "invalid", you never make any use of this address space until it is reallocated?
<maz>
kettenis: i.e. the PTs have been removed and there is no way the core can parse these page tables again?
<kettenis>
I think that's the case
<kettenis>
flushing the ASID during a context switch makes it work
<kettenis>
flushing the ASID when a reallocate it doesn't work
<maz>
what does your TTBR0 contain at the point where you invalidate on ASID reallocation?
<kettenis>
I'm not sure...
<kettenis>
will take a look at that
<kettenis>
it tends to be shell processes that crash so this maybe an issue with what happens during fork()
<maz>
if there is any valid level at all (not necessary leaves), you could end-up with intermediate walk entries being present, and that's no good.
<kettenis>
yup
<kettenis>
fell into that trap at some point
<kettenis>
but maybe it's not all fixed
<kettenis>
aggressive caching of TLB entries always leads to interesting bugs
<kettenis>
never got things quite right for PA-RISC
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<maz>
marcan: just realised another couple of nits: it'd be good if your APL-specific definitions were suffixed with the minimum EL at which they are accessible, just like any other AArch64 sysreg.
<maz>
marcan: also, SYS_APL_VM_TMR_MASK behaves like an enable, and no a mask (bit set to allow the interrupt). it'd be good if that was reflected in the name of the sysreg.
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<modwizcode>
marcan: can you link to the commit that explains the dsb thing?