marcan changed the topic of #asahi to: Asahi Linux: porting Linux to Apple Silicon macs | General project discussion | GitHub: https://alx.sh/g | Wiki: https://alx.sh/w | Topics: #asahi-dev #asahi-re #asahi-gpu #asahi-offtopic | Keep things on topic | Logs: https://alx.sh/l/asahi
<amw>
svenpeter: I've updated the Developer-Quickstart Wiki page with a brief description of using your m1n1 to get normal USB CDC-ACM link going. Hope it's reasonable
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<sven>
amw: nice, thanks!
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<sven>
kettenis: did you try what happens with the PCIe dart when you just ignore that vm-base/vm-size and allow "invalid" regions?
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<kettenis>
I thought I tried this at some point; maybe I messed it up
<kettenis>
the DART seems to work fine outside the vm-base/vm-size range
<kettenis>
I suspect that we do have to avoid the MSI address though
<sven>
interesting. so that vm-base might actually be a software thing sometimes
<kettenis>
I suppose this means we could shelve the dma window issue for later?
<sven>
i guess so
<sven>
s/guess/hope/ :)
<sven>
i've also seen "allow-subpage-mapping" in these "strange" DART device nodes
<sven>
maybe they are even another DART variant with more mysteries
<sven>
(there is something called "SMMU" which is ofc unrelated to the ARM SMMU under the display dart device node)
<kettenis>
so I played around a bit with the boundaries
<kettenis>
starting at 0 causes no issues
<kettenis>
and putting the window between 0xe0000000 and 0xf0000000 works as well
<sven>
i wonder why the reserve some space at the beginning then
<kettenis>
my guess would be to catch bugs
<sven>
oh.. good point
<kettenis>
a bit like not mapping the page at virtual address zero in normal user space
<sven>
maybe that's also the reason for the empty space between the pio and "normal" region arnd observed
<kettenis>
could be
<sven>
hm... there's an AES engine behind that dart-sio which is one the "strange" ones. i wonder if i can get that one up and running easily
<sven>
that would allow some easy tests
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<Necrosporus>
It seems RMS support letter is signed by more people that RMS defamation letter
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<sven>
heh, so it looks the aes engine works in bypass mode when i set yet another bit in the TCR
<sven>
i can't seem to setup pagetables for it though. something's certainly strange there
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<sven>
it complains that my TTBR is invalid but also sets another bit I don't know about in the error stage register
<kettenis>
how do you test the AES engine?
<sven>
i just reverse engineered the kext. i won't ever write any aes code for linux anyway :)
<maz>
marcan: as expected, the v4 branch broke KVM. and that's where things become interesting again...
<maz>
marcan: as you found out, mask/unmask of the guest timer wasn't working, which means I was running with the guest interrupts notionally disabled.
<sven>
kettenis: i always gets fault no matter what pagetables i setup in the DART. might be something rather dumb on my side.
<sven>
kettenis: but if this worked we could essentially pretend the AES engine is a DMA engine and actually figure out which addresses are good and what this pio stuff is all about
<maz>
marcan: but as it appears, I am still getting interrupts from these timers, despite the "disabled" state.
<maz>
marcan: conclusion: SYS_IMP_APL_VM_TMR_FIQ_ENA_EL1 doesn't do what we think it does.
<maz>
marcan: I have gutted out all the masking/unmasking code frop the AIC driver, leaving the two enable bits to 0.
<maz>
marcan: interrupts still fire just fine and my guests are happy.
<maz>
marcan: what I *think* this does is to turn the level interrupt into an edge.
<marcan>
what acks the edge in that case?
<marcan>
I do remember we need an isb after doing things like flipping TGE
<marcan>
to make that register work properly
<maz>
marcan: there is plenty of ISBs when flipping TGE. and I'm tegging the interrupt at EL2, not EL1.
<maz>
getting*
<marcan>
I'll have to do some more tests in m1n1, this is interesting
<maz>
yup. I've completely gutted the mask/unmask code from the driver, and I can still run guests, and getting interrupts on the host side.
<maz>
marcan: regarding your nVHE question: yes, the kernel runs at EL1 in that mode.
<maz>
it uses HVC to call into EL2 as required.
<maz>
kettenis: do you know if the DART translates the MSI doorbell? or does it let it through untranslated, a la x86?
<marcan>
maz: so that wouldn't work on M1 anyway, until I fix AIC to work in EL1
<marcan>
(I mean even without using KVM)
<marcan>
maz: if I had to guess, the PCIe endpoint handles the doorbell internally, but that's a guess
<marcan>
i.e. it never hits the SoC bus
<maz>
marcan: OK, so it is captured upstream of the DART. oddly similar to what Huawei did for their servers.
<marcan>
since the doorbell addr is the same for every endpoint, but they should have different MSI ranges
<marcan>
(I think)
<marcan>
and there's no reason to run that through DART
<maz>
marcan: as long as you don't have a two-stage translation on the IOMMU side, you're probably OK. once you start doing device assignment, things become really funny with untranslated doorbells.
<maz>
you have to make sure the guest IPA space doesn't overlap with the physical doorbell, which is a fixed point.
<maz>
anyway, not something we need to worry for the M1.
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<marcan>
heh, yeah
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<kettenis>
maz: the MSI doorbell address is programmed into the per-port host bridge registers
<kettenis>
and it isn't translated by the DART
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<kettenis>
apple seems to uniformly use 0xffff000 as the doorbell address
<kettenis>
but programming a different address works
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<marcan>
maz: I'm not seeing edge-triggered behavior in m1n1
<marcan>
turning off the mask bits, resetting the timer registers and scheduling them to fire, nothing happens
<marcan>
doesn't matter if I go into el0 or el1, still nothing
<marcan>
< sven> kettenis: but if this worked we could essentially pretend the AES engine is a DMA engine <- I wonder where you got that idea from :-)
<sven>
marcan: totally not the wii days, i swear! :P
<sven>
i don't think you can just not set encrypt/decrypt here though. so it's not that great for memcpying stuff around
<sven>
but once i figure out why that dart doesn't like my pagetables it should be good enough to get simple view into the iova space :)
<marcan>
yeah :)
<marcan>
(one of the first things I did with what became mini and the same proxyclient stuff in m1n1 was try control bits on the Wii AES engine and discover that if you don't set encrypt/decrypt, it just does a plain copy)
<sven>
didn't you also use that to figure out that weird paddr ^ 0x40 quirk? or was that just the nand hw?
<marcan>
that was the nand ECC syndrome calculation
<sven>
ah, right.
<marcan>
funny thing is after the "official" docs leaked a decade later, it was documented as + 0x40
<marcan>
so our docs are better :-)
<sven>
hah :)
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<kettenis>
sven: I would avoid including a dma-ranges dt-binding tweak if you're not going to rely in dma-ranges in your DART driver
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<sven>
the way i understand it is that dma-ranges is done completely outside of the DART driver anyway. this domain->geometry.force_aperture is on top of that and can just further limit the dma window.
<sven>
so essentially dma-ranges would be empty because in bypass mode 0x811112222 is a completely valid iova there. but once the iommu is switched to translate mode it's suddenly invalid
<sven>
this won't be another property in the device tree. it's really just if (domain->mode != BYPASS) force_aperture_to_32bit()
<sven>
but i can also leave it out if you think that's a bad idea as well
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<kettenis>
my point is that the clarification of dma-ranges isn't really related to the DART driver
<kettenis>
and potentially controversial since folks have different ideas about how it should be interpreted when there is an IOMMU
<svenpeter>
Ah, good point.
<svenpeter>
I’ll leave it out of the series then
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<sven>
huh. i think the dart even has some kind of feature to protect a range *within* a page
<sven>
or maybe i'm just doing something very dumb again :)
<marcan>
that would make sense for subpages
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