marcan changed the topic of #asahi to: Asahi Linux: porting Linux to Apple Silicon macs | General project discussion | GitHub: https://alx.sh/g | Wiki: https://alx.sh/w | Topics: #asahi-dev #asahi-re #asahi-gpu #asahi-offtopic | Keep things on topic | Logs: https://alx.sh/l/asahi
riker77 has quit [Quit: Quitting IRC - gone for good...]
ephe_meral has quit [Ping timeout: 240 seconds]
ephe_meral has joined #asahi
riker77 has joined #asahi
brandas has quit [Quit: quit]
brandas has joined #asahi
amw has joined #asahi
amw has quit [Ping timeout: 256 seconds]
amw has joined #asahi
amw has quit [Ping timeout: 264 seconds]
<modwizcode>
I found a random presentation on dmb vs dsb on arm and it implies my understanding is correct. dmb is enough to order the operations right, but because completion might not have happened there's a data race between the operations being observed remotely.
<modwizcode>
I guess the cache coherence stuff could theoretically not complete before the device write/read does? That still seems weird (and extermely unlikely)
amw has joined #asahi
amw has quit [Ping timeout: 264 seconds]
amw has joined #asahi
amw has quit [Ping timeout: 276 seconds]
<marcan>
modwizcode: I think I found that PDF, if it's the one I mentioned on the list on the v1 thread
<marcan>
but somehow linux gets away with dmb for DMA ordering, so... who's wrong?
raster has joined #asahi
odmir has joined #asahi
macc24_ has quit [Ping timeout: 272 seconds]
alvaro_fe has quit [Ping timeout: 276 seconds]
macc24 has joined #asahi
alvaro_f1 has joined #asahi
bgb has quit [Ping timeout: 240 seconds]
bgb has joined #asahi
ephe_meral has quit [Ping timeout: 240 seconds]
bgb has quit [Ping timeout: 256 seconds]
bgb has joined #asahi
bgb has quit [Ping timeout: 240 seconds]
bgb has joined #asahi
Tokamak has joined #asahi
<kettenis>
the way I read it is that dmb is enough to guarantee the ordering
bgb has quit [Ping timeout: 272 seconds]
<kettenis>
so if you want to guarantee that a flag in a descriptor gets updated after all the other fields, dmb would be enough
<kettenis>
but it doesn't guarantee that the memory access has completed
<kettenis>
so if you need to write to a register to tell the hardware that you updated the descriptor, you need another barrier