marcan changed the topic of #asahi to: Asahi Linux: porting Linux to Apple Silicon macs | General project discussion | GitHub: https://alx.sh/g | Wiki: https://alx.sh/w | Topics: #asahi-dev #asahi-re #asahi-gpu #asahi-offtopic | Keep things on topic | Logs: https://alx.sh/l/asahi
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<rkjnsn[m]>
Currently reading through the backlog, at I just wanted to say, as a supporter, I'd be proud to see the leader of project on the list, but it doesn't make sense to have the project itself sign on without it having a governing body of some time.
<arcsor5>
I personally don't understand the whole Stallman situation, I'll have to readup on it later on. Is this related to the GCC/LLVM thing or something else?
<arcsor5>
Whatever it is I support marcan on the issue, he's always right about everything
<rkjnsn[m]>
s/time/type/
<rkjnsn[m]>
… and just got to the part of the IRC log requesting a discontinuance of the discussion. Sorry about that.
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<marcan>
FWIW, I signed it last night (in personal capacity, with documented project association)
<marcan>
I don't think it makes sense to have the project sign the letter; it would be *accurate* to do so because the project doesn't have a governing body beyond "me", but it would seem to imply the existence of a larger consensus or governing body which is not the case, so it would be somewhat misleading
<marcan>
and on that front, since this hasn't been discussed yet: I'm operating on typical project founder BDFL capacity here as the founder of a young project, but I have no delusions of eternal personal control; I hope we can keep building a strong community and expect that, as things grow, some kind of governance structure will grow with the project as needed
<marcan>
(i.e. the "FL" thing is not so)
<marcan>
I'm going to coin BDFN (for now)
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<marcan>
(and it seems arcsor5 left, but I'm not always right, and shouldn't be assumed to always be right about anything)
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<marcan>
maz: other than the isb, did you have to fix the unmask on EOI behavior for guest timers? in the end you're using the irqchip masking path and the kvm code never touches SYS_APL_VM_TMR_FIQ_ENA_EL1 itself, right?
<marcan>
if that's the case then I think we can move the sysregs to the drivers, I *think* we won't have to deal with them in arch code. probably.
<maz>
marcan: that's right. I use the irqchip plumbing to get the AIC driver to do what I want, and I don't need direct exposure of the sysreg encoding.
<maz>
patch wise, there was just the two fixes for mask/unmask as well as the initial masking state.
<maz>
feel free to fold them into the main AIC patch.
<marcan>
the remaining issue was the irqd_irq_masked() thing you mentioned in the feedback
<marcan>
I was thinking of folding those in but leaving the vgic_set_kvm_info patch to you
<maz>
yes, please leave th vic stuff out. it depends on the previous patches which rework some of the infrastructure.
<maz>
which does something similar to what you'd need to implement.
<marcan>
yeah, I was just reading the core code to see how it didn't work
<marcan>
gotcha
<choozy>
Hello
<choozy>
Do you have certain intervals at which the Asahi kernel is pulling in a new kernel version from upstream? For a release tag?
<marcan>
choozy: there is no policy set in stone right now, but I intend to track at least kernel releases in general, and rebase on the latest RC before each patch submission cycle during submissions.
<choozy>
marcan: sounds good
<marcan>
v3 was based on the (cursed) 5.12-rc1; v4 will be based on whatever Mark's latest version of the FIQ stuff ended up on top of, since we have that as a dependency for now (the first submission cycle is weird, we have weird dependencies)
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<choozy>
Ah
<choozy>
Ah, the version where it could write swap all over the disk
<marcan>
yup
<marcan>
*we* don't care, we don't have disk :-)
<marcan>
but we will soon, nvme is next once I have v4 out, on top of sven's DART stuff
<sven>
that'll probably need at least another two or so versions fwiw. I just hope to have at least sane DT bindings for v2 :)
<marcan>
of course :)
<choozy>
Very nice
<marcan>
but it should at least work
<sven>
yeah
<sven>
not sure nvme is behind a DART though
<sven>
there's something called "SART" in the adt
<sven>
which might just be another iommu
<marcan>
hmmm
<sven>
yeah. it has " iommu-parent 0x00000086" which is " compatible sart,t8101"
<marcan>
interesting
<marcan>
"storage"?
<marcan>
maybe we can just bypass whatever that is in m1n1 for now
<sven>
yeah, possibly
<sven>
at least for the DART some of them can be bypassed
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<marcan>
also iboot needs to use nvme, so presumably this is initialized to some extent
<sven>
I couldn't look at the MMIO range previously because I didn't have the power management stuff figure out. but we can probably just turn it on now and see what's going on
<sven>
or maybe you could just finish that mmiotrace.c :P
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<maz>
does anyone knows whether the AIC has a trigger configuration (level vs edge)? I have a prototype MSI implementation, but we consider so far all interrupts fed to the AIC as level, which isn't a very good match for MSIs.
<maz>
or is the interrupt trigger baked and not configurable?
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<marcan>
maz: I haven't seen any register to that effect; I'm not sure how MSIs are supposed to work
<marcan>
maybe the PCIe controller does some kind of latching?
<marcan>
I think kettenis might know?
<maz>
marcan: maybe. I'll look on that side.
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<kettenis>
maz: so far I'm not treating the MSIs in a special way
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<kettenis>
however since OpenBSD uses interrupt priorities, I had to emulate those
<kettenis>
and my emulation was written with edge triggered interrupts in mind
<kettenis>
but I think the PCIe controller does some latching
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<marcan>
the question is what clears the AIC IRQ then
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<marcan>
if it's implicit in the ack in AIC (whether internally or via some feedback mechanism), then for all intents and purposes they are edge-triggered
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<kettenis>
wouldn't surprise me if that's the case and that this is hardwired behaviour
<kettenis>
I'm fairly confident that I'm not missing any MSIs
<kettenis>
as the OpenBSD xhci(4), bwfm(4) and bge(4) drivers work reliably
<kettenis>
regarding the MSI logic in the PCIe host bridge
<kettenis>
it seems there are 32 MSIs
<kettenis>
There is a mechanism to distribute those over the individual root ports
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<kettenis>
And Apple's device tree has properties suggsting that each port gets 8 of them
<kettenis>
(which means the last 8 are unused)
<kettenis>
but I'm running the bridge in a config where all 32 MSIs are shared among ports
<marcan>
kettenis: where the MSI value just maps to the index in AIC I presume
<marcan>
and yeah, if it all "magically" works then it must be edge-triggered
<marcan>
it might be interesting looking at the hardware state register at various points in the handler, see what level it clames those lines are at
<marcan>
and if it's high then goes low at some point
<marcan>
AIC_HW_STATE = AIC + 0x4200
<marcan>
that thing (it's a big bitfield, one bit per IRQ indicates level state)
<kettenis>
yes, "msi-vector-offset" in the ADT is the AIC interrupt vector that MSI 0 maps to
<kettenis>
#msi-vectors is the number of MSIs
<kettenis>
I suppose splitting the MSIs over the ports has some benefits for device isolation, maybe for VMs
<marcan>
I mean the MSI data value is just the index
<marcan>
right?
<kettenis>
right
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<kettenis>
so if MSI data is 0 it will trigger the AIC interrupt at "msi-vector-offset"
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<marcan>
makes sense
<kettenis>
if MSI data is 1 it will trigger "msi-vector-offset" + 1
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<marcan>
so yeah, I'm interested in what HW_STATE says during MSI handling
<marcan>
especially before and after the AIC event read
<kettenis>
let me see if I can somehow dump that
<marcan>
I guess something like read it unconditionally before the reason, then if it was an MSI, read it again after the reason and actually print both values
<marcan>
(if the MSI offset is 32-aligned then all you need to read is a single 32-bit word)
<kettenis>
right
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<marcan>
going to get some sleep, will check the backlog tomorrow :)
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<kettenis>
marcan: the bit corresponding to the MSI interrupt is set in HW_STATUS before reading INTERRUPT_ACK
<kettenis>
and cleared after reading INTERRUPT_ACK