marcan changed the topic of #asahi to: Asahi Linux: porting Linux to Apple Silicon macs | General project discussion | GitHub: https://alx.sh/g | Wiki: https://alx.sh/w | Topics: #asahi-dev #asahi-re #asahi-gpu #asahi-offtopic | Keep things on topic | Logs: https://alx.sh/l/asahi
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<marcan> maz: I did mention that the mask registers don't work if TGE=1, right? so if Linux leaves the guest timers active when context switching out of the VM, that won't work
<marcan> maybe that explains the "edge triggered" thing you saw?
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<maz> marcan: not really. I ran a little experiment to try a find when the ISR_EL1.F bit gets cleared.
<marcan> fyi, I ended up adding EL1 support to the AIC driver since it turned out pretty easy (just guarding some stuff and mapping the IRQs differently in the translate function)
<marcan> just pushed that now
<maz> marcan: it just takes a read of CNTP_CTL_EL0 to see the bit drop to 0.
<marcan> it's good enoug to boot after a chainload.py --el1 to m1n1, with nosmp (nosmp because I don't virtualize CPU spin-up, so the secondaries come up in EL2 and that explodes)
<marcan> huh
<marcan> are you sure it's not a synchronization issue?
<marcan> though we do issue an isb...
<maz> nah. there are more ISBs that you can imagine in that sequence.
<marcan> so wait, this is with FIQs trapped to EL2, right?
<maz> FIQs routed to EL2, not even with any virtualisation going on.
<maz> read ISR before reading CNTP_CTL, F is set. read it again, it is clear.
<marcan> and with everything idle, and the timers masked, setting up a timer to fire you see it raising a FIQ in EL2?
<marcan> with TGE=0?
<maz> TGE=1, I'm on the host.
<marcan> yeah, it doesn't work in the host
<marcan> the guest timer masking only works with TGE=0
<maz> that's not the point. FIQ acts as a edge triggered interrupt, and the ack is the read of the CNT registerse.
<maz> registers*
<maz> I'm talking about the HV registers here (though the guest regs behave the exact same way).
<marcan> maz: wait wait, are you saying that *all* the timers are *always* edge^triggered?
<marcan> *-
<marcan> like, the HV ones too?
<maz> unless I've messed up my experiment (not unlikely), it looks like it.
<marcan> I just tried it in timer_test.py and I don't see that
<marcan> the ISR_EL1 bit remains set (FIQ masked in DAIF)
<marcan> I will say I *used* to think the mask register did some weird edge triggered stuff, until I realized I was missing an isb after setting TGE=0, and what I was seeing it was it not taking effect until after the first exception was taken
<marcan> which is why I keep asking about isbs :-)
<marcan> maz: is it possible that TGE gets flipped to 1 at some point with the guest timers still firing? in that case you would get FIQs delivered to EL2
<marcan> though that's about the masking, I certainly can't explain any kind of edge-triggered-like behavior for the HV timers
<maz> marcan: we do restore the timers with TGE=1, always. but if it was a level, that interrupt would keep firing forever, because I'm not using this mask *at all*.
<maz> and it doesn't.
<maz> nothing in the interrupt handler clears the timer.
<maz> it stay active.
<sven> marcan: you'll do nvme next, right? any objections if i take a stab at i2c and that ti chip then to get closer to working usb? or is there anything else you think should come first?
<marcan> maz: wait, I just found something
<marcan> remember we had the vGIC issue with not being able to control the hardware state when using the funny list register, right?
<marcan> I just realized at at least it *does* listen to the mask register
<marcan> so we can at least mask a firing timer, but we still can't inject a non-firing one
<marcan> anyway, that aside
<marcan> https://mrcn.st/p/AYXJ2jlI here is some exhaustive testing
<marcan> I'm definitely not seeing the ISR cleared when I read the CTL register
<maz> marcan: and you don't see the timers firing when the mask is set to 0?
<marcan> correct
<marcan> *iff* TGE=0
<marcan> of course, if you restore the timers with TGE=1, that will cause them to fire
<marcan> well, firing as in ISR_EL1 is zero
<marcan> of course the timers fire in the timer registers
<marcan> they just don't raise a FIQ
<maz> right. but they fire *once*, not as a level.
<maz> otherwise I wouldn't be able to make forward progress.
<marcan> actually, I'm not even seeing them fire when masked if TGE=1 either
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<marcan> maybe I'm confusing myself
<maz> I wonder if I'm being tricked by the FIQ handler dealing with both HV and guest timers *in that order*.
<maz> if the mask is actually a mask, and that the guest timer is pending, we are still going to process the interrupt.
<maz> and we do that irrespective of the masking.
<marcan> I tried actually firing a FIQ (DAIF clear) and just reading (not writing) the timer registers there, and I still get a FIQ storm
<marcan> and... yeah, the AIC code should not be dispatching guest IRQs if the masks are set, should it
<marcan> that's a bug
<maz> let me fix that locally and see what happens...
<marcan> pushed a fix to the v4 branch
<marcan> also, the register name was wrong; it's _EL2, not _EL1
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<maz> marcan: local hack fixed it indeed.
<maz> marcan: apologies for dragging you on the wrong path!
<maz> marcan: tested on top of v4, all working now.
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<marcan> maz: np, it was my bug after all. thanks!
<marcan> maz: should I send out those two VHE fix patches at the head of v4, or do you want to keep discussion of those to your thread?
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<goosteady> This is such an exciting project. I got my wife an M1 Air and am so jealous but I am not running MacOS.
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