22:35 <cphealy> With the Vivante GPUs, I see in the public block diagram that there is a PE (pixel engine) downstream from the shader. Is the PE responsible for detiling on platforms such as the GC2000 when the display controller can only support linear buffers?

22:38 <flto> cphealy: RS does the detiling on GC2000

22:39 <cphealy> What role does the PE serve then?

22:39 <flto> its what writes out pixels while rendering (does blending,etc)

22:40 <cphealy> http://media.bestofmicro.com/Z/H/401741/original/VIVAUShader.png

22:40 <cphealy> I don't see the RS in the above block diagram. Is it part of the PE?

22:42 <cphealy> Also, what does RS stand for?

22:46 <flto> not sure what it stands for, I think its "resolve".. its *probably* the 2d pipeline in that diagram (is this diagram for GC2000?)

22:51 <cphealy> The diagram is from here: http://www.vivantecorp.com/index.php/en/media-article/news/224-20130920-toms-hardware-vivante-vega-article.html

22:51 <cphealy> My assumption was that the diagram was showing the equivalent of what is in the i.MX6q where there are three GPUs. GC2000 for 3D, GC355 for Vector Graphics, and GC320 for 2D.

23:02 <flto> yeah that makes sense, but somehow I don't think those 3 share the same PE.. the RS probably just isn't in this diagram

23:37 <cphealy> ack