00:02 <_whitenotifier> [Glasgow] Success. The Travis CI build passed - https://travis-ci.org/GlasgowEmbedded/Glasgow/builds/504465129?utm_source=github_status&utm_medium=notification

03:43 <marcan> whitequark: ply works with classes: https://github.com/johnyf/astutils/blob/master/astutils/ply.py

03:43 <marcan> well, you can make it work with classes anyway (writing a couple base classes like that)

03:44 <whitequark> okay

03:44 <marcan> could just depend on astutils instead of ply directly

03:44 <whitequark> LALR is usually not a good choice for things other than programming languages

03:44 <whitequark> a lot of people use PEG, and well, i dislike PEG, but it'd probably be good enough if we had to adopt some one parser

03:44 <whitequark> if there's some fast enough Python PEG runtime

03:45 <marcan> not getting any hits

03:45 <marcan> oh there are some

03:45 <marcan> https://github.com/erikrose/parsimonious

03:47 <whitequark> https://github.com/erikrose/parsimonious#status

03:47 <whitequark> hrm

03:47 <whitequark> oh right

03:47 <whitequark> PEG parsers can't stream

03:47 <whitequark> e.g. the SVF parser is streaming

03:47 <whitequark> you can feed it a gigabyte of SVF just fine right now

03:48 <whitequark> see this is why i keep handrolling shit

03:48 <whitequark> but it's not sustainable

03:48 <whitequark> most people can't just write something like the SVF parser and if they can it's too much effort

03:48 <whitequark> which is fair

04:35 <whitequark> marcan: so, stupid idea

04:40 <marcan> whitequark: btw, the PCAs arrived, can probably test tonight

04:40 <marcan> and if they work I'll update the design

04:43 <whitequark> excellent!

06:03 <whitequark> esden: btw, once you have your revFrankenC, i would be grateful if you sent a nonzero number to me. any "extra" glasgows i end up with will be wired in various continuos integration configurations, or at least that's the idea.

06:03 <whitequark> some might end up doing things like exposing Yamaha synthesizers to the web also

06:38 <esden> whitequark: will do! :D I have to see how many I actually end up putting together before ordering the new and updated boards. :)

17:02 <marcan> whitequark: ok, validated the PCAs (well one of them)

17:02 <marcan> no measurable leakage on cold power up

17:03 <marcan> I have some leakage when powering down after powering up the Vio rail... and it had an inverse relationship to the previously set voltage... and I just realized that's because VFB sticks when EN is lowered, lol

17:03 <marcan> might want to change that to set the DAC voltage to 0 when powering down (after a safe threshold) to get rid of up to 15mV or so of leakage through that feedback resistor

17:04 <marcan> I had a failure to set pulls initially, but after probing it went away, and I can't reproduce it

17:04 <marcan> I can only assume it was a short or some other issue with my patchjob that went away

17:19 <marcan> oh, my addr connection is loose, lol

17:19 <marcan> that would explain the failure

18:15 <marcan> for reference: https://photos.app.goo.gl/drsN2iKxdL14izjS7