<azonenberg>
Might be the smallest nyan cat made to date
<swkhan>
omg so cute
<azonenberg>
200um high and 600 long
<azonenberg>
pixels are 20um square
<azonenberg>
this is 100x magnification
<azonenberg>
he's patterned in about 2um of SP24 photoresist over 200nm of copper
<swkhan>
you made that at home? o_O
<azonenberg>
evaporated onto a glass substrate (microscope cover slip)
<azonenberg>
Almost
<azonenberg>
I did the copper deposition in a lab on campus
<azonenberg>
all of the lithography, as well as the photoresist deposition, was at home
<swkhan>
i work in a lab on campus too but it doesn't have all the facilities i'd like
<azonenberg>
I overetched a bit (notice the green areas expanded beyond the holes in the mask)
<azonenberg>
turns out even five seconds in full strength SC2 is overkill for going through a couple hundred nanometers of Cu
<azonenberg>
i'm gonna dilute it like 50:1 for the next etch (tonight) so it's slow enough to be controllable
<azonenberg>
I'm also having issues with focuser drift on my microscope objective
<azonenberg>
over the 10-ish minute exposure the stage will move down by a couple of microns
<azonenberg>
and blur really small features
<azonenberg>
i get good results with the 10x objective (so my 200um laser-printed mask becomes 20um per pixel) but the 40x is blurred beyond usability
<azonenberg>
Which school is your lab at btw? I'm a PhD student at RPI
<swkhan>
well we're at nasa ames. it's a weird collaboration with a lot of different universities
<swkhan>
i know a friend who will be going to RPI next year =)
<swkhan>
it's a weird collaboration because everyone just gives the facade of collaborating but doesn't actually take many steps to actually get work done
<azonenberg>
Lol
<azonenberg>
And nice. whats he studying?
<azonenberg>
I did my undergrad work at RPI too (computer science)
<azonenberg>
graduated last spring and i'm now just starting my doctorate
<azonenberg>
But most of my work, as you can probably tell, is leaning toward the EE side of things
<swkhan>
i think he's studying materials science
<azonenberg>
In that case he'll probably be playing with the same SEM and evaporator i've been using
<swkhan>
ooh
<azonenberg>
RPI has more than a handful of SEMs
<azonenberg>
there's a zeiss supra 55 FESEM in the cleanroom (which is expensive to get on but the best on campus)
<azonenberg>
right next to it there's another zeiss, dual beam SEM / FIB
<swkhan>
wow a fib
<azonenberg>
then outside the cleanroom inthe mat sci department there's an old jeol tungsten-filament SEM, a newer jeol FESEM
<azonenberg>
Complete with two little pics at top right
<azonenberg>
doesnt like empty space in PCBs
<smeding>
me neither! all that copper just dissolving into your etchant, such a waste
<smeding>
silly PCB artwork is good for the environment!
<azonenberg>
lol
<kristianpaul>
considering crosstalk between layers.. well :)
<azonenberg>
Well i'm not making the board myself - its a 4-layer design
<kristianpaul>
oh
<azonenberg>
3.3V and ground planes are in the middle
<bart416>
smeding, you're not answer my question
<azonenberg>
marked by + and - vias
<bart416>
Are you enrolled at Delft or not?
<smeding>
bart416: i just said, i am
<azonenberg>
kristianpaul: any overall thoughts on the board?
<smeding>
bart416: however, don't even have my P yet
<smeding>
close though :p
<bart416>
Just answer yes if people as if you're there >_>
<kristianpaul>
pic32 is to load bitstream?
<bart416>
Also why the hell are you complaining then
<bart416>
At least you guys have the equipment to do something
<smeding>
hm?
<azonenberg>
kristianpaul: Lol its overkill for that
<bart416>
We have to beg for new oscilloscopes >_>
<smeding>
i was... complaining?
<azonenberg>
the plan is for the pic32 to be the main CPU and the FPGA to be a GPU
<azonenberg>
as well as offloading heavy computation to it
<bart416>
"<smeding> wish i could play in our university clean room (DIMES at Delft UT)"
<bart416>
^Sure sounds like it :P
<smeding>
not so much a complaint as something i would like to do at some point
<kristianpaul>
pci32 is U1 right?
<smeding>
it looks like fun, anyway
<azonenberg>
Yes
<azonenberg>
fpga is U2 - 200k gate spartan-3a
<smeding>
but yeah, facilities are definitely very, very good
<azonenberg>
in 100vqfp
<azonenberg>
U5 and U6 are 1A linear regulators
<kristianpaul>
i dont see to much wires between board fpga and pic, os i asume trougput is low?
<kristianpaul>
s/to/too
<azonenberg>
for the 3.3 and 1.2v rails
<azonenberg>
and actually its an 8-bit parallel bus
<azonenberg>
which could be clocked at up to 40 MHz
<kristianpaul>
he i jsut countent a nibble ;)
<azonenberg>
Its not a 64-bit bus or something like that
<kristianpaul>
8 bits seems okay then
<azonenberg>
heck, the whole pic is only 64 pins
<kristianpaul>
sure sure
<azonenberg>
They do have a 100 pin version with a 16 bit parallel port
<azonenberg>
but realistically i dont need that much bandwidth
<azonenberg>
when i outgrow this board in a few months / a year ish i'll do a 6- or 8-layer design with a 256FTBGA fpga and a softcore CPU (no external MCU)
<azonenberg>
and a few hundred megs of SDRAM
<kristianpaul>
the sram of the fpga is enought for you app i guess too
<azonenberg>
Yeah, i considered an external ram but couldnt route it on 4 layers while also having the IO resources i wanted
<azonenberg>
the main purpose of the fpga is to run the video output
<azonenberg>
800x600 VGA in text mode
<azonenberg>
curses-type interface
<kristianpaul>
that GPIO is what for?
<azonenberg>
Seemed a shame to pay $100 for three 4-layer boards and not get access to all the FPGA pins :P
<azonenberg>
so i figured i'd break 'em out to a ribbon connector in case i needed them for something in the future
<kristianpaul>
considering is just video out vias cross under it..
<azonenberg>
this is meant to be a "play around" board, its not for any specific purpose
<kristianpaul>
ah ok
<azonenberg>
They're gonna be relatively low speed signals
<azonenberg>
and there's power and ground planes between themn
<kristianpaul>
:)
<azonenberg>
everything is single-ended on this board
<azonenberg>
except for USB
<azonenberg>
the v2 design will be using more differential stuff like TMDS video
<kristianpaul>
he, the cap smile footprint :)
<azonenberg>
that isnt a cap
<azonenberg>
its just a smiley
<kristianpaul>
lol
<azonenberg>
i like throwing little pictures in that last unused few mm^2 of a board
<azonenberg>
note the stuff under it? Not hooked up to anything either
<azonenberg>
thats a 7-stage CMOS ring oscillator :P