14:47 <mardinauskas> Multiple solutions, all that matters is when you go out of order, previous instructions did not schedule due to deps. you go right to the wfid 5. issue it, then fetch counter is at 1, column change however is done when the mentioned values equal in the queues. So you gotta skip some instructions to do branch emulation in queues, and skipping is done via indirection.

14:50 <mardinauskas> as far as the chip is concerned, it will increment fetch counter if something was issued then the perfect way is to use back to back loads the same address, and indirection toggler

14:52 <mardinauskas> all the thing is, that there is an enourmous amount of variations how one wants to solve it, to be able to read a single solution you need to know rules, and hence i put lot of theory into code

14:52 <mardinauskas> and comments

22:25 <mardinauskas> it is *pretty* good how the hardware logic is laid out, you should not ask for any better. And this is the both for CPUs and GPUs. And it is not difficult today to make a competing arch either.