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<rellla>
heyo lima guys, i need your help ;)
<rellla>
i tried to implement ppir fddx/fddy and got a reasonable codegen imho - piglit tests (for example shaders@glsl-derivs) still fail, see http://imkreisrum.de/piglit/glsl-derivs/
<rellla>
for comparision i fed the offline compiler with the shader and get the following code:
<rellla>
my guess is, that it has sth to do with the sync. i don't actually understand, what it does, but maybe it's a problem that dFdx and dFdy are divided into 2 instructions?
<rellla>
(in case you wonder, i hardcoded dFdx to scalar slot and dFdy to vector slot for the testing)
<rellla>
thats the one issue i have. the second one, personally more interested in, what are the general conditions i have to follow, if i want to combine some instructions after the scheduler?
<rellla>
for example that would be instr 001 and 002 in my test case, which contain dFdy and dFdx, both reading from $0 and writing to $1 with different components used.
<enunes>
rellla: right now there is no general automatic combining, if you want to (or must) combine them, you have to combine yourself
<cwabbott>
and yeah, sync is required for all instructions that do derivatives and texturing, since threads have to share their results
<cwabbott>
you seem like you're doing it correctly
<rellla>
i disabled nir_lower_wpos_ytransform temporarily to avoid the load_uniform op, but this should not be the problem
<rellla>
maybe there is some other thing missing still... texture based maybe?
<rellla>
enunes: regarding the combination, i guess i have to think about the conditions, when the recent instruction can be combined the last one.
<enunes>
rellla: I think it's not necessary to care about this now unless it's required
<enunes>
which looks like it isn't
<rellla>
isn't it an advantage, when instr count goes down?
<rellla>
or do you just want to say, "the are much more important tasks now" :)
<enunes>
yes but right now it would only be some sort of premature optimization, at some point I think there should be some attempt to do an overall pass combining things when possible
<anarsoul>
rellla: if disassembly looks correct but it still doesn't work you should check actual binary
<anarsoul>
maybe some "unknown" fields differ
<anarsoul>
(that's how I discovered that branch instruction has another "next instruction length" field (for the case when branch is taken)
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