03:51 <mardinator_> by violently manipulating with internals of my life from/by people who are known scammers to me , which is stalking , arranging something that does not belong to you by not honoring the rules, the minimum sentence is the relatives after you many generations get known and treated as scammers along with their anchestors, i won't try to hide that this is something i have targeted, so the human kind would know who is and was the

03:51 <mardinator_> fellon.

03:59 <mardinator_> when a king of senseless hallucinations manipulates the world that without any reason that mart sees delusions, himself not getting really close to anything legal in competition to the higher standards, i think one genuinly diserves to be identified as a scammer, which in my book is the most worthless garbage, what you pump you get.

04:02 <mardinator_> i myself since common sense is nothing to do with energy resources per individual, would not had tried to even make sense to people who can not make any sense anyways, however since you try to coordinate my life via violative way picking a fight everywhere, this type of behavior needs to be registered.

04:04 <mardinator_> in other words, issue does not rely on how much sense you make, but issue relies on the violation and coordination of possibly superior lives life internals, this is manipulation i do not tolerate

04:12 <mardinator_> so you have every right over your lives to do what ever you wish if you follow the laws, in rare cases when some other individual does not seem to obey to laws, rights are given to sentence another life, in modern world, just a crooked individual that does not mean that you have rights over lawful individuals life, since this does no longer belong to you, does that make sense to you?

04:24 <mardinator_> if you would had followed such specification and not having feed estonian scammers and crooked terrorists, i also would not had bothered and interferred about how much sense you make.

04:26 <mardinator_> generally i do not feel this is any of by business how much someone makes sense and the way one wants to live his/her life never starting a war over me would had resulted me closing eyes at this.

04:27 <mardinator_> Will Smith tell me do you beat up in the shower, you cross the line, privacy laws, that is not any of your god damn business scammer.

04:30 <mardinator_> taken from indepdence day, where congressman was killed and accidentaly video tape found its way to another mans pocket, they stalked the ones who had the video tape, actually the bird filmer accidentally taped the murder

04:32 <mardinator_> and passed the video tape to will who did not know having it, so they used military equipment running so called training ops violating the privacy laws to stalk will charecer

04:32 <mardinator_> *character, as this was not allowed all in all, the crew was brought down

04:34 <mardinator_> ouh shit not indepence day, but Enemy of the state was this great movie

04:36 <mardinator_> and as an equivalent to my situation this crew who coordinated illegally my life, after some group of leftovers humiliated me and presented their sex heroics, should be braught down from the high positions in the infra.

04:45 <mardinator_> when you are emplyed by countries infra to sentence terrorists or lawless individuals or and fellons/scammers but you instead use the force on innocent people or in this case victims of the terror, this diserves the firing of such crew.

04:49 <mardinator_> so this is how it goes, and that is it, in the programming the sizes of ROBs have always been given to the developers in microarchitectural papers

04:50 <mardinator_> so 72macro-ops for athlon is the rob entry size, 80 for cortex-a9, 40 for pentium pro, pentium II, pentium III, 126µops for p4 etc.

04:50 <mardinator_> short list of the capabilities of some arm/amd/intel cpus

10:55 <mardinator_> https://www.diva-portal.org/smash/get/diva2:831071/FULLTEXT01.pdf page 41. has the measurement, so when 4ns pr instruction is full pipeline latency 128 ops/insts during 1 ns is the short pipeline latency, since the underlying GPU schedules to 8 cuda cores, it has 512 single elements, how much does one operation consume time?

10:55 <mardinator_> it will be 128/8 i.e 16 and 1000/16

10:55 <mardinator_> hence 62.5 picoseconds per instruction

10:58 <mardinator_> but since they had 3ghz clock you need to divide this result with 3 yet

11:00 <mardinator_> hence you can be entirely sure, that during 50ps whatever you do, the alu is fully executed, on loadbased schdueling over lsu

11:06 <mardinator_> this yeah round about makes sense, cause when you google --- adder delay "ps" the results of propagation and full delays are around 20-60ps

11:14 <mardinator_> so when you type CLA or ripple carry adder to google wikipedia is one of the linked page, i assume CLA is used mostly on chips from long time ago, does not matter, can be manchester or kogge-stone, but not ripple carry

11:15 <mardinator_> because this one is not very parallel type of adder

12:00 <mardinator_> so 32-bit CLA =11 gate delays, and 64bit cla 13 gate delays according to berkeley university info

12:00 <mardinator_> https://en.wikipedia.org/wiki/FinFET

12:01 <mardinator_> https://www.eit.lth.se/fileadmin/eit/courses/eti135/slides/02-TechnologyScaling.pdf

12:03 <mardinator_> so 130nm one gate delay is slightly below 5picoseconds

12:06 <mardinator_> gtx580 should be 40nm nodes so 20ps is entirely correct for aly to graduate

12:12 <mardinator_> http://www-inst.eecs.berkeley.edu/~cs150/sp06/HWs/hw8soln.pdf on page 5 those are listed

14:37 <mardinator_> rest of it maybe even you know better! I think that GCN feeds vec4 instructions as four different vec1 ones right so either on the same registers but different wavefront bases, or possibly alshs using different registers out of ?

14:38 <mardinator_> *also, out of 256

14:40 <mardinator_> hence the 4ns measure, because hw does not use vectors transparently, the next instruction is definitely not going to be decoded

14:43 <mardinator_> as opposed to being limited to some clock syncrhonous hw flops, it is just the matter that pipeline does not decode vec4 instructions as separate vec1s faster then 1during a cycle

14:45 <mardinator_> so whatever you tried to say that GCN is SIMT instead of SIMD and it can not do what nvidia SIMD does is not quite correct.

20:06 <mardinator_> as most here on the channel are ARM fellows, then on some CPUs tomasulo does not work out, gpu only fast accel offload possible then. In particular anything that is in-order core, like anything below cortex-a8 included. And also 64bit variant of in-order core named a-35

20:06 <mardinator_> https://users.elis.ugent.be/~leeckhou/papers/hpca17.pdf

20:07 <mardinator_> psge 7 table for reference of the problems with them.