00:34 <xdarklight> pigiron: interesting, it's working for Xogium with 5.3.5 and this config: http://ix.io/1YiV

00:45 <xdarklight> also chewitt reported that it's working for him with that config: https://github.com/LibreELEC/LibreELEC.tv/blob/master/projects/Amlogic/linux/linux.aarch64.conf

00:49 <pigiron> Oh wow. I'll grab those and recompile. Could be something with my SoC also... who knows. Thanks!!

00:53 <xdarklight> I didn't have time to ask him but there was also this message: <chewitt> see if this works https://test.libreelec.tv/LibreELEC-AMLGX.arm-9.80-nightly-20191006-96737bf-odroid-c2.img.gz

00:54 <xdarklight> so in case it doesn't work for you with your self-built kernel you can try that image to rule out compiler weirdness

00:55 <pigiron> Great! I'll grab that also. Thanks to everyone!

01:13 <GNUtoo> narmstrong: I've looked at the reference you pointed me to (https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic/commit/c3a558382a710823b13c45ee699a746ce7d423d7) when asking about what were the binaries

01:13 <GNUtoo> according to https://github.com/repk/gxlimg BL2 might be related to DDR init

01:14 <GNUtoo> but beside that I didn't find what bl31.bin and bl301.bin did

01:14 <GNUtoo> (and acs.bin)

01:14 <GNUtoo> the answer might be in u-boot though

08:13 <repk> GNUtoo: bl31 is secure monitor or the ATF runtime, it runs in EL3 and dispatch SMC to secure/non-secure world. bl301 is a part of the SCP firmware. On meson the SCP is run by a microcontroller (cortex-M3) and handles power related stuff.

08:13 <repk> see https://trustedfirmware-a.readthedocs.io/en/latest/ for more on that

08:18 <repk> So BL1 is the CPU boot ROM code executes in SRAM and lunch BL2 which initializes DDR load all remaining firmwares (BL30 SCP, BL31 secure monitor, BL32 TEE, BL33 u-boot) in it. Then BL31 installs the secure monitor sends bl30 to SCP, and gives control to BL32 (if exists e.g. OPTEE) and BL33 (usually u-boot). Then u-boot loads boots linux.

11:12 <narmstrong> And acs.bin are the system parameters to configure the ddr controller

11:13 <narmstrong> repk: bl31 also loads bl301 right ?

11:14 <repk> narmstrong: maybe I wrong but I think bl2 load bl301 from sd,emmc,nand,... to DDR. Then BL31 sends it to SCP internal memory

11:14 <repk> I'm*

11:17 <narmstrong> Ok

21:30 <GNUtoo> repk: thanks a lot