08:39 <narmstrong> xdarklight: the needle trick to unsolder ?

18:08 <xdarklight> narmstrong: yep, so fewer of these things have to die

18:22 <repk> jbrunet: xdarklight thanks for your reviews. No that I have reread the documentation I do get what you mean that this should not be a clock gate. I'll make a driver for axg-mipi-pcie phy, but because I have no way to test the mipi thing it will only do pcie mode and thus will be fairly small. Is that a problem ?

18:24 <jbrunet> I don't think it should be a problem if it is clearly explained. It would be good to have a bit of information about this though

18:26 <repk> agreed

18:27 <jbrunet> Also we will need to coordinate the change with the clock controller so that :

18:27 <jbrunet> 1. We remove mipi-enable clock as well

18:27 <jbrunet> 2. Change region mapped by the controller so you can map the it for your MIPI Phy driver. If the region is dedicated to the PHY, it should never have been mapped by the clock controller to begin with

18:28 <jbrunet> If the things controlled by those bits are actually clock, nothing forbids you from creating clock in that PHY driver, I would even it is highly appreciated

18:31 <repk> right I don't think those things are actually clock but rather gate the CML output of PCIe pll.