11:24 <repk> narmstrong: So now that I am moving MIPI clock in a shared phy driver for AXG's PCIE following jbrunet recommandations, I may be able to merge the has_shared_phy logic of g12a vs axg and just use phy subsystem for both. Do you seen any objection on that ?

11:40 <xdarklight> repk: I don't know the detailed register layout of the MIPI PHY / PCIe PHY / PCIe controller on AXG but one of my questions during the review of the PCIe controller driver was "can we move the PHY logic to a PHY driver?"

11:41 <xdarklight> repk: so my answer is: go for it unless you see any problems ;)

11:43 <repk> xdarklight: ok perfect, thx