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23:09
<
xdarklight >
narmstrong: thank you so much for the diagram, that makes things MUCH clearer!
23:10
<
xdarklight >
narmstrong: I think "hpll_clk_out" in the Meson8m2 tree is the output of the PLL, meaning it's actually hdmi_pll_dco
23:12
<
xdarklight >
(if I multiply hpll_clk_out with lvds_od to get back to the PLL rate then the values go wrong)
23:14
<
xdarklight >
also the naming "hpll_lvds_od" is what REALLY confused me before I had your diagram. I thought that it was related to the LVDS video output...
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