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<stdint> bertje__, no actually, but you may have a try on the dwc2 reset patches
<bertje__> @stdint thx, we already applied several of those patches to make the OTG port work properly in host mode… is there a patch that specifically deals with gadget issues?
<bertje__> @stdint the weird thing is that uboot correctly uses the dwc2 as a peripheral, but the kernel does not … no interrupt is firing (uboot uses polling)
<bertje__> @stdint it also seems like setting dr_mode has no effect, when we try to set it to peripheral
<stdint> bertje__, I don't think it should happen, anyway, just have a try
<bertje__> @stdint the OTG port works properly in host mode after we applied the reset patches
<bertje__> @stdint but not in device mode
<stdint> have you tried update your kernel
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<bertje__> @stdint not yet, what mainline version do you recommend we try
<stdint> next-20170303
<bertje__> @stdint ok i’ll try that
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<mmind00> bertje__: if you look in the archives of the linux-rockchip mailinglist you can see someone else also having issues it seems:
<mmind00> bertje__: I didn't follow that closely, but there seem to be some Synopsys people helping to investigate the issue he has
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<bertje__> @mmind00 wondering where this “couldn’t set device mode” is coming from
<bertje__> @mmind00 rockchip guys say on their side it is working but then they are not using mainline (?)
<mmind00> bertje__: nope Rockchip themself are providing mainline patches, but do seem to use a 4.4 derivative as base-kernel for current devices
<bertje__> @mmind00 i’m using 4.8 … would this be source of this problem?
<mmind00> bertje__: and the dwc2 has seen quite some changes over the last kernel releases, so there is the possibility that something broke
<bertje__> @mmind00 broke between 4.4 and 4.8 you mean?
<mmind00> bertje__: don't know - haven't cared about device mode at all yet ... so maybe in a first step compare the logs from Francesco with your own, to see if its the same issue
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<stdint> anyway, I would confirm that later
<stdint> bertje__, in my memory it works for me at 4.9
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<LongChair> stdint: morning
<LongChair> saw the mpp PR ? :)
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<bertje__> @stdint what board and chipset are you using and what .dts file?
<stdint> firefly release
<lkcl> stdint: hmmm... iinteresting. ok so i have the firefly booting again (4.9rc1 but that's ok)
<stdint> lkcl, does the kernel I sent you not work?
<lkcl> what i'd done is modify the u-boot sdram base frequency down to 200mhz in order to get my board booting
<lkcl> stdint, one sec: the kernel's not the problem
<lkcl> stdint: so, what i've established is: if you modify the sdram initial frequency to below 300mhz, neither my board *NOR* firefly will boot from external MicroSD.
<stdint> it would causing a huge performance problem
<lkcl> stdint: i'm not concerned about performance, i'm concerned (a) about power consumption and (b) actually booting :)
<lkcl> sdram_params->base.ddr_freq = 290000000;
<lkcl> if ((sdram_params->base.dramtype == DDR3 &&
<stdint> I see
<lkcl> "arch/arm/mach-rockchip/rk3288/sdram_rk3288.c"
<lkcl> that's mainline u-boot.
<lkcl> so, if that startup value is set to 300000000, firefly boots from microsd, no problem.
<stdint> what I want to said is that a lower frequency would leading a performance issue
<lkcl> below 300000000, even if it's 299999999, it won't work
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<lkcl> stdint: understood and a lower performance is perfectly acceptable. the card *has* to be below 5.0 Watts absolute maximum.
<lkcl> and 4 DDR3 x16 RAM ICs operating at say 533mhz is going to use about... 40% of that power budget.
<lkcl> leaving nothing for the actual CPU.
<stdint> I don't think the rk3288 is the suitable SoC for that
<stdint> it doesn't support DVFS of the RAM
<lkcl> well, here's the problem: at 300mhz for the rk3288-eoma68 board, it still doesn't boot.
<lkcl> if, instead, i use this:
<lkcl> rc4 ddrinit ../rkbin/rk32/32_LPDDR2_200MHz_LPDDR3_200MHz_DDR3_200MHz_20150318.bin
<lkcl> followed by USB-upload of u-boot, then that *does* work
<lkcl> as long as the ddr_freq is set to around 280mhz or less
<lkcl> BUT
<lkcl> if i set even to 300mhz, i get this:
<lkcl> Col detect error
<lkcl> DRAM init failed!
<lkcl> which, clearly, is bad.
<lkcl> and indicates that the DDR3 RAM isn't stable.
<lkcl> stdint: sooo... about the only thing left i can try at this point is to put on different lower-spec'd RAM ICs. lower top speed (800mhz, 1033mhz) and/or lower capacity.
<lkcl> *sigh*
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<LongChair> stdint : i also had another question regarding the RAM performance on tinker. Looks like when phh tested ram throughtput on his RH3288 device, he woudl have something like 1.1G/s, when tinker would have like 840M/s. According to you would that also be a clocking frequency issue or just that the Tinker RAM chip are crappy ?
<stdint> none of them
<stdint> I would suggest you having a try on gstreamer
<LongChair> what would explain then memory bandwith differences ?
<LongChair> and where do i get the latest gstreamer ?
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<mrjay> bertje__: just to confirm usb otg bug on rk3066
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<stdint> LongChair, well at github
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<LongWork> stdint: i'll try to build gstreamer and check it
<LongWork> still the memory performance difference is not related to gstreamer
<stdint> yes, but I wonder whether you configure the kernel or u-boot properly
<stdint> if you don't use the gstreamer to feed back the performance but using the ffmpeg
<stdint> it would be hard to comparing
<LongWork> i will try to get gst built in my debian
<LongWork> i suppose there is no package already built ?
<stdint> there is
<stdint> but I am not sure about whether the latest is uploaded
<stdint> I could send you one if you want
<stdint> also the mpp
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<LongWork> sure
<LongWork> a package would be nice
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<lkcl> stdint: i know what the problem is. i went to an 8-layer 1.2mm PCB, from a 6 layer *1.6* mm design. the impedance *HALVED* from 90 ohms to 50 ohms and that's more than enough to stop the DDR3 lines from working.
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<paulk-collins> oh boy, I wouldn't want to be EE
<lkcl> paulk-collins: :)
<lkcl> i never said i was! don't tell no-one, paul.. :)
<paulk-collins> haha
<paulk-collins> (it's actually my course of studies)
<lkcl> ah! then i seeerriously need your help
<paulk-collins> I didn't say I'm good either ;)
<lkcl> haha
<paulk-collins> but yeah, I can try
<lkcl> i have to make an effort to rescue this board
<lkcl> at around 280mhz the DDR3 RAM can still run.
<lkcl> push it to 300mhz and it falls over
<paulk-collins> so bad impedance adaptation/matching?
<lkcl> impedance of all the DDR3 tracks is 50 ohms, 3.5mil wide
<lkcl> *sigh* yeahhh
<paulk-collins> can't the dram controller be configured to match that specific impedance?
<lkcl> this is all in PADS btw. by changing the dielectric constant to 2.2 i can get it up to 70 ohms
<lkcl> i have _no_ idea!
<lkcl> it didn't occur to me to even find out if that was possible
<paulk-collins> yeah I think it's usually how it's done
<lkcl> huh.
<paulk-collins> not sure though, I just have vague memories of it
<lkcl> hmmm... ok... sooo... let's take a look in the dram source for rockchip u-boot
<paulk-collins> lkcl, some reading regarding allwinner: v
<lkcl> paulk-collins, taaa....
<lkcl> /* DS=40ohm,ODT=155ohm */
<lkcl> zqcr = 1 << ZDEN_SHIFT | 2 << PU_ONDIE_SHIFT |
<lkcl> 0x19 << PD_OUTPUT_SHIFT;
<lkcl> 2 << PD_ONDIE_SHIFT | 0x19 << PU_OUTPUT_SHIFT |
<lkcl> ah HA!
<paulk-collins> hehe
<paulk-collins> well done
<lkcl> that looks like it's the right sort of thing to mess with
<paulk-collins> indeed
<lkcl> no idea what the fuck i'm doing but hey
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<paulk-collins> :)
<lkcl> ok apparently it's noodles-eating time. thanks paul. i have a line of enquiry that doesn't involve throwing out $1k's worth of hardware.
<paulk-collins> neat!
<paulk-collins> happy noodles-eating
<ayaka> what do I miss?
<lkcl> ayaka: lol - a bowl of noodles with coriander and bean-sprouts for one...
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<lkcl> ... oh and paul noted that it *might* be possible to recover this first board by changing the zqcr values in "arch/arm/mach-rockchip/rk3288/sdram_rk3288.c"
<ayaka> I can't help much about the hardware
<ayaka> that is why I suggest you coming here first
<ayaka> but it would be fine to find out problem
<lkcl> yeahh i know... but there are certain unavoidable hardware constraints that, in retrospect, i would still have to do the exact same thing anyway.
<lkcl> we need to use FR4 (it's lower-cost), the PCB _has_ to be 1.2mm, and it _has_ to be 8 layer
<lkcl> given that those constraints could not change even if i visited RC's HQ first...
<ayaka> anyway a noodles with coriander looks like a Hakka style food in Taiwan
<lkcl> ayaka: haha it was just something my partner marie made, we are in a reaaaally small room 4m x 4.5m nominally for students
<lkcl> when i move back here next month it will be to a 3-room apartment for (gosh, shock) a whole $USD 400 (!!)
<lkcl> sooo let's see if there's a TRM page for the memory controller...
<lkcl> off of
<ayaka> I am not sure, but if you have any problems just ask
<lkcl> ayaka: i could really really do with some help picking the right settings for ZQ
<lkcl> /* DS=40ohm,ODT=155ohm */
<lkcl> zqcr = 1 << ZDEN_SHIFT | 2 << PU_ONDIE_SHIFT |
<lkcl> 2 << PD_ONDIE_SHIFT | 0x19 << PU_OUTPUT_SHIFT |
<lkcl> that's just not possible (without just simply guessing) to interpret
<ayaka> anyway, I think the documents of the memory controller would be release in a few week or month
<ayaka> I have received that version
<lkcl> ahh that would be helpful to have them sooner than that
<ayaka> after I have my dinner, I would look the document
<lkcl> but in theory i can wait - it puts back plans for release of everything until i have a working rk3288 prototype
<lkcl> ok :)
<ayaka> btw, Having a taste on porn of Taiwan black pig
<lkcl> i will ... eek! you so did _not_ mean "porn of taiwan black pig" :)
<lkcl> that is *definitely* an auto-spelling correction error lol
<ayaka> it is the amazing thing if you could accept its sweat as it is lou mei
<ayaka> pork
<lkcl> whew lol
<ayaka> I want to kill the iOS
<lkcl> haha
<lkcl> you're using *what*?? :)
<ayaka> iPad
<lkcl> ahh. yeah first thing i do with any proprietary OS: switch off autospell...
<ayaka> I can't. btw, I could tell you a lot of delicious food in Taiwan and foreign usually don't know and can't be found on super market
<lkcl> ayaka: oo niiice
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<lkcl> ayaka yes please. we seem to be doing well here in shenken
<ayaka> Ah, I know where you are
<ayaka> I would send you a email later
<lkcl> ok :)
<lkcl> we are NOT going to try that horrible-smelling tofu :)
<ayaka> yes I know, even I can't accept it at the first year
<ayaka> I begin to eat it at the second year
<IgorPec> wens: Fix enable bit offset for hdmi-ddc module clock not working for me.
<ayaka> lkcl, sorry, what do you want to know about DMC?
<lkcl> ayaka: ideas on how to set ZQ
<lkcl> ayaka: in u-boot-rockchip
<lkcl> "arch/arm/include/asm/arch-rockchip/ddr_rk3288.h"
<lkcl> there are some #defines ZDEN_SHIFT, PU_ONDIE_SHIFT etc
<lkcl> which, in "arch/arm/mach-rockchip/rk3288/sdram_rk3288.c"
<lkcl> line 865
<lkcl> there is a comment "DS=40ohm, ODT=155ohm"
<lkcl> all related to "ZQCR" - ZQ control register i presume
<ayaka> lkcl, I am not very familiar with DMC, let me give you a index of that
<ayaka> I will search ZQCR
<lkcl> ack good idea
<lkcl> DDR3
<lkcl> ZQCFG looks good, DDR2 doesn't
<lkcl> can't be that one
<lkcl> or if it is, it's misnamed
<lkcl> "arch/arm/include/asm/arch-rockchip/ddr_rk3288.h" looking at rk3288_ddr_publ struct would help
<ayaka> lkcl, DDR_PUBL_ZQ0CR0
<lkcl> yep that's definitely the right one.
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<lkcl> ayaka, this is something like what i need:
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<ayaka> lkcl, yes I want try to export that register for you
<lkcl> ack thx
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<ayaka> lkcl, sent to mailbox
<lkcl> thxman
<ayaka> you are welcome
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<lkcl> ayaka, ahh iiinteresting, they do manual setting of impedance values
<lkcl> that's what 1<<ZDEN_SHIFT is about
<lkcl> soooo i will try setting ZCAL bit (this will be tomorrow)
<lkcl> and not use ZDEN (manual config)
<lkcl> if that works then it is good to go, i can always try manual config later
<FUZxxl> naobsd: ping
<wzyy2> = =It seems it find the reason that why we get bad gpu on-screen performance in x11....
<wzyy2> it seems i..
<wzyy2> modesetting in 1.18.4 don't support page flip, so it will wait vblank in "swapbuffer".
<ayaka> our kernel does not support that I think
<ayaka> I have used kms sink to verify that before
<wzyy2> I don't know, yao said we support page flip.
<wzyy2> Android framwork is using page flip.
<ayaka> then driver is configed properly
<ayaka> it would report it is not supported
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<LongWork> i'm looking for a divider ... seems i have a 4 between aclk & hclk setup .... but can't fin it back here
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<LongChair> phh :
<LongChair> hclk_hevc 0 3 297000000 0 0
<LongChair> aclk_hevc 0 5 594000000 0 0
<LongChair> but no dice ... still same perf
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<FUZxxl> naobsd: ping
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<bertje__> so we got the otg port on rk3288 working in device role
<bertje__> we had to go to 4.10 mainline (we were on 4.8.1 mainline)
<bertje__> on the firefly reload board it’s also important to disable the regulator for the OTG VBUS otherwise it won’t work in device mode
<bertje__> the OTG_ID pin is pulled high on the firefly reload core module which means it is always in device mode, unless host mode has been set via dr_mode
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