<micken>
when is it safe to power off boot cpu? PMU reg 0014?
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<micken>
ah now my gic code is broken :D
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<micken>
RISC OS 987MB
<micken>
Cortex-A72 Processor
<micken>
\o/
<micken>
half not working
<micken>
GIC is not working so
<micken>
seems like only core 0 gets interupted
<micken>
micken: rtfm
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* flacks
grabs popcorn
<anarsoul>
flacks: any luck with fixing reboot issue?
<flacks>
no, just testing different versions of u-boot/bl31 before diving into the code
<flacks>
have yet to build linux for this chip, will probably start with ayufan's tree in an attempt to help identify the whereabouts of the regression
<flacks>
what I don't get is that it'll sometimes reboot successfully. it rebooted successfully twice just now
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<anarsoul>
flacks: yeah, it looks like some regulator issue but I checked all the regulators and they're fine
<anarsoul>
also I'm not sure if it's a regression, I've never seen it working on mainline
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<pcbBob>
Can someone tell me why webchat.freenode.net disconnects me after like half an hour?
<pcbBob>
What IRC client are you using?
<micken>
irssi
<micken>
robmur01: one thing is puzzling me, how do I connect the cpu/cluster to gic , make the pe to accept spi's
<micken>
and is GICD the first segment in the GIC block?
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<flacks>
robmur01: can you link to the miniloader and ATF you're using? feel free to PM
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<robmur0121>
micken: on RK3399 you definitely have GICv3 (GIC-500), it just has the GICv2 compatibility mode option too ;)
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<robmur0121>
I don't know off-hand the exact sequence of stuff to enable, but I'd hope it's mostly just a case of tweaking whatever existing setup to target a different CPUIF
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<robmur0121>
then set the affinity of SPIs to the appropriate MPIDR (e.g. 0x100 instead of 0)