ChanServ changed the topic of #linux-rockchip to: Rockchip development discussion | IRC log http://irclog.whitequark.org/linux-rockchip | Community GH https://github.com/linux-rockchip | Rockchip GH https://github.com/rockchip-linux | ML https://groups.google.com/group/linux-rockchip
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<hurricos> vagrantc: Hey! I found you. Can I ask some questions about veyron boards?
<vagrantc> hurricos: i don't know much, but i have one
<hurricos> Ah, that's enough :) SEO pushes irc logs very high so you know more than enough ... I have what claims to be a veyron jerry, out of a CTL J2; it gives access to the 4MB flash SOIC
<hurricos> Can you confirm that as a chromeos device the soic contains coreboot, and the eMMC has depthcharge?
<vagrantc> likely conmtains coreboot and depthcharge
<vagrantc> contains...
<vagrantc> it's not impossible to put something else there, i think there may be a u-boot port for it
<vagrantc> but out of the box i'd guess coreboot/depthcharge
<hurricos> (u-boot patches for it)
<hurricos> My goal: I have some scrapped veyron jerry's that I'd like to flash the SOICs on so they can easily boot e.g. from a USB.
<hurricos> I'm surprised to hear depthcharge on the SOIC as if I'm not mistaken coreboot is not the one initializing graphics
<hurricos> which usually means blobs which are big
<hurricos> The libreboot guide for the C201 (veyron_speedy) mentions requiring root in ChromeOS which I do not have. Since I don't have a servo header to solder onto the board to get serial I've been assuming I would need something which I can build to boot over USB by default, which could then load up a linux kernel, modeset, boom, I can fix things in eMMC.
<hurricos> so I'm curious to know how you have your veyron configured.
<vagrantc> i had to flash the SOIC
<vagrantc> well, i think the first time i did it from chromos somehow ... but then botched u-boot testing at some point
<hurricos> Yeah, that's what confuses me a bit -- I am unsure where CrOS state is stored and would want a reliable way to not rely on it.
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<hurricos> OK. I think I got how I'll build the replacement -- I think I can do what Google does. See https://irclog.whitequark.org/linux-rockchip/2018-06-04#22253176
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<mrjay> i'm keep getting this: https://pastebin.com/hbwCk7aP
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<stefan_> HI, trying to boot RK3399 from SPI but having troubles. I am now using mainline U-Boot 2020.10 and the latest ATF and am trying to build the tpl + spl + u-boot.itb
<stefan_> I am stuck at SPL
<stefan_> U-Boot SPL 2020.10-dirty (Dec 04 2020 - 12:27:11 +0100)
<stefan_> Trying to boot from MMC2
<stefan_> mmc_load_image_raw_sector: mmc block read error
<stefan_> Trying to boot from MMC1
<stefan_> mmc_load_image_raw_sector: mmc block read error
<stefan_> SPL: failed to boot from all boot devices
<stefan_> ### ERROR ### Please RESET the board ###
<stefan_> Any idea what am I doing wrong?
<wens> missing SPI support?
<wens> you might want to check the commits that enable SPI boot
<wens> b587acc6b1fb rockchip: rockpro64: add SPI boot
<wens> 1831191b18d7 roc-rk3399-pc: Add SPI boot
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<stefan_> I do have these
<stefan_> CONFIG_SPL_SPI_FLASH_SUPPORT=y
<stefan_> CONFIG_SPL_SPI_SUPPORT=y
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<stefan_> CONFIG_SPL_SPI_LOAD=y
<stefan_> and I did change u-boot,spl-boot-order
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<dvergatal> stefan_: which board?
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<stefan_> dvergatal: it is one custom board, but has SOM-RK3399 v2
<stefan_> I made some progress
<stefan_> But now I am getting error
<stefan_> unrecognized JEDEC id bytes: 00, 81, 10
<dvergatal> stefan_: i dunno how about you but i had a problem with firefly-rk3399 for over a month because of bad dts files for this board in u-boot mainline
<dvergatal> first try to but using sd card
<dvergatal> if it wil work for you than try to work with spi
<dvergatal> more over stikonas has some experienc in booting from spi
<dvergatal> stefan_: he has also a blog on which he has described it all
<stikonas> this one...
<dvergatal> stefan_: yeah
<dvergatal> stikonas: hi
<stikonas> hi, but I probably wouldn't know those JEDEC errors
<dvergatal> stikonas: by the way i have succeded with mine firefly :]
<stikonas> dvergatal: nice :)
<stikonas> what was wrong?
<dvergatal> stikonas: you won't believe it
<dvergatal> very easy fix:]
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<dvergatal> but stupid
<dvergatal> hmmm gone;p
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<dvergatal> back:P
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