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<oliv3r>
ssvb: ok i'll read up on that mail thread, so i'm wrong to assume the hansg was ported to 3.4. So if i take his initial calibration stuff and back-ported it should be reasonably ok
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<oliv3r>
bbrezillon: hey guy!
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<bbrezillon>
oliv3r: hi
<bbrezillon>
oliv3r: I guess you want to talk about the NAND controller driver :)
<bbrezillon>
oliv3r: I haven't had a lot of time to work on it lately (I do this on my spare time), and I must admit that endless discussion to decide whether NAND timing requirements (for non ONFI chips) should be defined in the device tree or in a NAND device table (in the code) is not helping in motivating me
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<oliv3r>
bbrezillon: nah, just wanting to show my encourangment :)
<oliv3r>
you are doing a great job for sure :)
<oliv3r>
have you monitored cpu load of the nand driver? since we lack dma
<oliv3r>
what do you expect the cpu cost would be? and have you done any performance tests and compared it to the libnand driver?
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<oliv3r>
ssvb: ok i read the mail thread, but it would make me think that all the a10 tests are ' done' or you want more reference points?
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<bbrezillon>
oliv3r: No I haven't any stress test or perf test on this driver, but you should definitely ask hani if he did
<bbrezillon>
oliv3r: regarding what I expect, I'd say it shouldn't consume that much CPU because we're already using NAND controller buffers to transfer ECC block of data (from 512 or 1024 bytes)
<bbrezillon>
which means it only cost up to X (X = page_size / ECC_block_size) DDR to internal SRAM transfers for each page write
<bbrezillon>
I've worked on atmel's NAND controller (on at91 SoCs), and in this controller you have to transfer byte per byte (write it to a specific register), so I'd say we're pretty lucky with the sunxi NAND controller ;-)
<oliv3r>
hehe :)
<oliv3r>
so DMA is not a hugely crittical part to have?
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<oliv3r>
it's 'nice' and a little faster/cpu efficient, but not a huge deal then?
<bbrezillon>
I'd say, there a lot of chance it is faster without DMA
<bbrezillon>
but surely less efficient in CPU usage
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<mnemoc>
ijc: license patch pushed. sorry for the delay
<ijc>
mnemoc: Awesome, thanks! (no worried about the delay!)
<oliv3r>
and i'll fix the 3.4 code in your branch to match hansg's more closely
<oliv3r>
it's getting nice and hot though :)
<oliv3r>
3 second burn :p
<oliv3r>
(aewsome statistic, i know :)
<oliv3r>
i'm doing lima-tester + cpuburn, i guess that's 'good enough' to generate the most heat?
<ssvb>
just the textured-cube program (without memtester) together with cpuburn-a8 would generate the most heat
<oliv3r>
ah ok
<oliv3r>
well the cube just dissapeared and i got a black screen :(
<oliv3r>
(i'm an fedora 19 image i had laying around)
<oliv3r>
with 3.4.79
<ssvb>
hmm, has it failed or just the display has blanked?
<oliv3r>
i just did a systemctl stop display_mager
<oliv3r>
i'm not sure yet
<oliv3r>
how do I disable blanking again?
<oliv3r>
i think we had a trick for that
<ssvb>
consoleblank=0 in the kernel command line
<oliv3r>
ah right ok
<oliv3r>
i'll fix that, recompile u-boot with your fix
<ssvb>
u-boot-sunxi should already have it
<ssvb>
just enable the scaler mode in fex
<oliv3r>
this is new stuff! I haven't heard abou the dram host port changes
<oliv3r>
oh, bummer :p
<oliv3r>
ok
<oliv3r>
what about the 480 Mhz of the lime, is that the default clock? looks nice and high
<oliv3r>
with the latest u-boot changes that's 'without problem' kinda deal?
<ssvb>
?
<bbrezillon>
oliv3r: I don't know exactly, and I can't test it right now, but I hope it does not exceed 5%, because most of the time spent in reading from/writing to NAND is spent waiting for the NAND chip to actually do what we ask for
<oliv3r>
i don't remember the default memory timings for the lime, i thought it was something around 385 MHz
<oliv3r>
bbrezillon: so the DMA is not hugely important and won't offer a HUGE benefit
<oliv3r>
that's great to hear, as that means we may be able to use the mainline kernel afterall
<ssvb>
oliv3r: it has been always 480mhz on a10-lime, and with the 16-bit memory interface, having high dram clock speed is important
<bbrezillon>
oliv3r: I don't think so, but again, I've never done any test to prove it :-)
<ssvb>
oliv3r: we may clock it a little bit higher eventually
<ssvb>
oliv3r: do you have the a10-lime pcb revision A or revision B?
<oliv3r>
ssvb: rev C :)
<ssvb>
oh
<oliv3r>
is that bad?
<ssvb>
do they have schematics available?
<oliv3r>
not initially, but I think they said they would do it after sending them to me
<oliv3r>
so they should be online now
<oliv3r>
i have a nand enabled lime :)
<ssvb>
I just wonder whether they have changed the ZQ resistors again or left them alone
<oliv3r>
wow i have al ot of backreading to do to learn more about the ram stuff
<oliv3r>
you know a lot about this shit :p
<oliv3r>
prob more then AW engineers :)
<oliv3r>
if you can give me the R and C numbers, i'll check
<oliv3r>
ssvb: looks like the memory bandiwth + high res issue is 'fixed' though?
<oliv3r>
or is it mearly a workaround?
<oliv3r>
still not perfect, some jerking and jarring, but very watchable
<ssvb>
the shaking should be fixed
<ssvb>
but some tearing is to be expacted unless we sync to vblank
<ssvb>
when using DEFE, we only have two layers instead of four, so it's a bit of a headache for the display driver developer to optimally manage resources at runtime
<ssvb>
oliv3r: about the ZQ resistors, A and B revisions of A10-Lime use something else instead of 240 ohm and both are different
<ssvb>
oliv3r: looks like Olimex used the hardware approach to solving the impedance matching problem instead of configuring it in software
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<ssvb>
oliv3r: Lime A and Lime B are very different boards if we are looking at configuring the optimal DRAM parameters...
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<oliv3r>
ssvb: they 're-layed out' the memory lines?
<oliv3r>
ssvb: it looks really much better though, it is only tearing year
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<ssvb>
oliv3r: not necessarily changed the memory lines, but replaced the resistors with different ones
<oliv3r>
ah ok so a 'minor' change
<oliv3r>
well they changed the silk screeen so something surely changed on the board
<oliv3r>
ouch, it's friggin' hot :(
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<ssvb>
oliv3r: how much? have you measured the temperature?
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<oliv3r>
no, i'm working on the code side, and the FLIR camera will arrive somwhere this afternoon :)
<ssvb>
ok
<oliv3r>
right, compiling, lets hope it works
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<oliv3r>
ssvb ok i also get a 82.4 C temp now
<oliv3r>
how do i calibrate/change it exactly?
<oliv3r>
or just 'leave it as be' and record it just to see the linearity?
<oliv3r>
i can record reported temp + measured temp + freq.
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<philippe_fouquet>
hi
<philippe_fouquet>
some body can help me with livesuit 306 and ubuntu 14.04 64bis?
<philippe_fouquet>
it worke fine withn ubuntu 12.04 but not with 14.04
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<oliv3r>
ssvb: i think lima-tetured-cube crashed :(
<oliv3r>
or cpuburn actually
<oliv3r>
fg
<oliv3r>
it was getting really hot to be fair
<oliv3r>
the internal diode was telling me 105C
<oliv3r>
though that is wrongfully calibrated as you mentioned
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<oliv3r>
ssvb: lima-textured cube is no problem, it keeps going at 20% cpu load, cpuburn crashes
<oliv3r>
not sure if it's a power issue, but i'll find that out soon
<oliv3r>
i'll use a bigger power supply
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<ssvb>
oliv3r: sounds very much like an overheating issue to me
<ssvb>
cpuburn-a8 alone is rather mean to the hardware
<ssvb>
but if combined with the lima textured cube demo (which is not competing with the cpuburn program for cpu cycles), the power consumption skyrockets
<ssvb>
oliv3r: hmm, is it really reporting 105C under load? how much did it show after cold start on the idle system?