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<patap>
112
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<apritzel>
mripard: Salut, where did the clock patches you just applied actually end up?
<apritzel>
Or didn't you push it yet?
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<mripard>
I haven't pushed it yet
<mripard>
there's some merge conflicts I need to solve
<mripard>
and I don't have the time to do so right now
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<zoobab_>
trying armbian build, they do have a profile for H3
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<apritzel>
mripard: no worries, could you give me a heads-up when you push something. I plan on sending a v2 of the A64 series, based on your latest stuff (including this clocks rework)
<apritzel>
but more towards the end of the week or early next week, so no real hurry here
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<mripard>
apritzel: I still have a few comments I haven't had the time to give you :/
<mripard>
mostly the critical-clocks patch can now be removed
<apritzel>
yeah, which is good
<mripard>
and please use the H3 bus gates, like we already discussed on IRC
<apritzel>
instead of the new, more DT oriented driver?
<mripard>
and there's probably a bit more things on that compatible stuff, as I see new mails from you
<mripard>
but I haven't looked at them yet :/
<mripard>
yeah
<apritzel>
take your time on that, I don't really need to rush this
<apritzel>
I still would like to have the generic bus gates driver, though ;-)
<apritzel>
happy to discuss this on the list, as soon as find some time
<apritzel>
*as you*
<mripard>
yeah
<mripard>
I'll try to do that this evening
<apritzel>
Merci!
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<Rambler44>
I wonder about one thing. Does ARM in general use a lot of resources to transfer files or is it just that I've always used enough I/O and RAM to never notice=
<WarheadsSE>
0o
<WarheadsSE>
transfer files how? You're quite generic.
<Rambler44>
WarheadsSE Haha, I know. Lets say sequential read then?
* WarheadsSE
sigh
<WarheadsSE>
to memory?
<WarheadsSE>
rsync?
<WarheadsSE>
cat ?
<WarheadsSE>
transfer from where to where, via what
<Rambler44>
Ok, let's just bring up some specific examples.
<Rambler44>
I am transferring a file over the NIC on LAN to another device.
<WarheadsSE>
"you seem to take a while getting here." "where is here?" "north america"
<Rambler44>
Unecrypted multiaccept HTTP
<Rambler44>
The RPI 1 can't even dream of ever reaching its 100Mbps
<Rambler44>
As a matter of fact it seems to struggle at 50Mbps
<WarheadsSE>
It's choking the USB bus, that Pi.
<Rambler44>
It's all on one USB 2.0 right.
<WarheadsSE>
And, that MMC controller is crap.
<Rambler44>
It has DDR2 RAM, and I think the new model also has so. It has some MicroUSB adapter and Broadcom CPU.
<Rambler44>
I think the RPi 2 can do the 100Mbps though
<WarheadsSE>
you best metric is to load a ~300MB file into tmpfs
<WarheadsSE>
the bcm2835 vs bcm2836, the only real change is the arm cpus
<WarheadsSE>
the busses are all the same
<WarheadsSE>
same mmc, same usb (single), etc
<Rambler44>
I think that was the reason people were so hyped over 64-bit ARM CPUs coming out
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<Rambler44>
Allwiner, Amlogic, Rockchip etc all these are in line to be released. With zero support whatsoever included.
<WarheadsSE>
how..
<WarheadsSE>
64 bits does not mean absolutely better.
<Rambler44>
I don't know, wider bus to put 8 GB RAM into a shitty machine.
<Rambler44>
Hehe
<WarheadsSE>
The thing that actually knowledgable people are excited about is the ARMv8 generation jump
<Rambler44>
Higher RAM frequencies?
<WarheadsSE>
don't care
<Rambler44>
Oh RAM running two times as fat can make a difference.
<Rambler44>
fast*
<WarheadsSE>
get me 2GB or 8GB? doesn't matter really. Faster RAM? meh. get me a better interconnect.
<WarheadsSE>
two time as fast on a thinner bus won't help
<Rambler44>
So the Pine64 ones have a ARMv8 right?
<Rambler44>
I don't know enough but I think that I saw something suspicious in the "confidenti al"
<Rambler44>
datasheet
<Rambler44>
Such a nice bus
<Rambler44>
32-bit bus
<apritzel>
Rambler44: the Pine64 CPU cores are proper 64-bit ones, but the rest of the SoC is just what they had on the shelf - so some original 32-bit design
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<catphish>
interesting: http://linux-sunxi.org/SATA claims that DATA on the A20 can read at 200+MB/s but only write at 45MB/s, i wonder if this is the same issue i'm running into with Ethernet
<apritzel>
Rambler44: in fact the limitation of the A64-DRAM controller to support at most 3GB sounds a bit suspicious to me - but would make sense if the bus is limited to 32-bit
<Rambler44>
One must also not forget the fact that they are using a tablet SoC
<Rambler44>
Maybe a hardkernel with a new Amlogic CPU could feature 4 GB RAM in the foreseeable future, if anyone even needs it.
<Rambler44>
The first phone with Snapdragon 820 made by Samsung features 4GB LPDDR4
<apritzel>
Rambler44: have the seen the Amlogic 905 and the Odroid C2?
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<Rambler44>
It depends on their choices. Maybe people won't need more than I think they are aiming for 2 GB RAM?
<Rambler44>
Maybe there will be a C2+ with 2 GB RAM.
<Rambler44>
4*
<Rambler44>
So they are putting 4 GB LDDR4 onto 32-bit dual-channel bus width
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<catphish>
is there some public documentation for the armada 385?
<catphish>
Turris Omnia uses it, cant find any public documentation though :(
<catphish>
vpeter: thanks, that's exactly what i was looking for, sorry for my apparent inability to use google!
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<Rambler44>
Isn't all the cheap Chinese vendors simply using the core license and ARMs own cores, imagine how it would be like with custom cores.
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<tkaiser>
catphish: The cheapest Armada 38x device to play with might be WRT1200AC
<catphish>
tkaiser: yeah, thats what i'm considering buying :)
<tkaiser>
And I'm still curious whether you find something regarding GMAC and sunxi SoCs
<tkaiser>
With A20 for example we have the problem that SATA is the bottleneck in one direction and GMAC in the other.
<tkaiser>
But maybe it's just stupid to expect high I/O and network bandwidth from tablet SoCs.
<catphish>
tkaiser: so, right now, here's the results i'm seeing when i send 1Gbps of traffic to the A20 and try to loop it back: TX: 955,853.42 Kb/s RX: 722,924.52 Kb/s, the GMAC receives 68,463 packets per second, and fails to transmit 16,830 per second in reply because the TX buffer is full
<catphish>
the PC is transmitting 85,060.94 packets per second (of which 68,463 arrive), the SoC is managing to loop back 64,167.83 PPS
<tkaiser>
Which A20 board are you using? Banana Pro IIRC?
<catphish>
yes, banana pro
<catphish>
yes, seems my tx performance (722Mbps) matches your measurement
<catphish>
but my other numbers were nonsense
<catphish>
let me start over and produce a sendible report
<catphish>
*sensible
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<tkaiser>
catphish: Which tools do you use for your measurements/tests?
<catphish>
on my PC i'm using bwm-ng, which just reports linux's NIC counters, on my banana pro i'm running totally proprietary code that measures TX and RX packets
<catphish>
i'll post proper results in a minute, just eating :)
<catphish>
my code on the A20 counts how many packets it receives, and counts how many it successfully transmits, the difference represents packets dropped because the TX buffer was full when it tried to transmit
<tkaiser>
Is this (TX buffer full) caused by a bug in silicone or is this software?
<tkaiser>
Sorry, I'm a NOOB on this layer :)
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<catphish>
tkaiser: that's the part i'm not sure of, all the software is my own, it's very simple, so its possible that the silicon is slow, but also possible that i haven't configured some optimizations correctly
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<catphish>
basically my code puts packets in a special area of memory and tells the NIC to send them, when that memory is full it has to stop sending
<KotCzarny>
basically chip is better at receiving data than sending be it sata or eth
<catphish>
KotCzarny: my current theory is that DMA is slow at reading data from DRAM, but i have literally no evidence for this
<catphish>
i was hoping someone understood it better than me
<KotCzarny>
reading memin too little chunks?
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<catphish>
KotCzarny: possibly, i'm not sure
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<KotCzarny>
i wonder if its fixable in software somehow
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<catphish>
that's what i've been trying to do
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<catphish>
so far i have no ideas though
<KotCzarny>
can you control caches?
<KotCzarny>
mem reads? any dma?
<catphish>
i can control caches
<KotCzarny>
check what distrubs mem reads
<catphish>
to clarify, the GMAC (Ethernet) is working entirely on DMA
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<KotCzarny>
can you do it without dma?
<catphish>
nope
<catphish>
it only works on DMA
<catphish>
(afaik)
<KotCzarny>
is dma controllable/configurable at all?
<catphish>
i'm going to go read the manual on that now
<KotCzarny>
maybe there is some errata regarding it
<catphish>
i'm mostly glad to hear i'm not the only one running into this limit
<KotCzarny>
maybe its not a bug but a feature
<catphish>
(700Mbps)
<catphish>
i'm hoping i can tune it, just not sure what to change :(
<KotCzarny>
ie. tablets mostly consume (receive) data
<KotCzarny>
ie. asymmetric data process split
<catphish>
KotCzarny: actually the NIC has options to prioritize RX over TX
<catphish>
it's possible with my tests i'm simply running into an aggregate tx + rx limitation
<catphish>
i could write some code that purely transmits at maximum speed
<catphish>
this will be interesting, but not useful to my use case (router)
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<KotCzarny>
yeah, looks like chip cant read and write data at once, and reading/receving is prioritized (think adsl)
<catphish>
KotCzarny: in theory, one can choose whether to prioritize read over write
<KotCzarny>
can you check what is the max for tx?
<KotCzarny>
would be swell if you could do similar code for sata
<catphish>
i dont know much about sata, but i could look into it
<catphish>
i'll try to do RX only and TX only ethernet anyway
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<kadamski>
I'm trying to access some of the registers on H3 SoC using /dev/mem and mmap. It works great for GPIO registers and some others but for some reasons, I can't get it to work with some registers
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<kadamski>
for example H3 User manual mentions that at the base address 0x01f01c00, offset 0x144, there is a CPU_CLK_GATING_REG
<kadamski>
but reading this address gives me 0 and no writes are accepted to it
<kadamski>
I would expect this register to contain 0xf at the end as all 4 CPUs are enabled
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<kadamski>
what may be th reason for that ?
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<mripard>
kadamski: either the parent clock is shutdown, or the register is only accessible in secure mode
<mripard>
or the device is maintained in reset
<kadamski>
mripard: shutdown clock - that's what I thought when I was trying to access CIR registers (even though I think I did enable all the clocks/gates as described in the manual)
<kadamski>
but what could be the clocks for CPU_CLK_GATING_REG ?
<kadamski>
since CPUs are running, this should be operational. or am I missing something ?
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<mripard>
which kernel are you running ?
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<kadamski>
mripard: linux-next from couple days ago
<mripard>
then linux doesn't access those registers
<mripard>
and the kernel itself might not even be able to
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<kadamski>
could you please elaborate a little?
<mripard>
linux runs in non-secure mode, u-boot leaves a bit of code behind running in the secure world to do the CPU bringup
<mripard>
the only thing the kernel does is signal to that u-boot code that it needs to bring up or down the CPUs
<kadamski>
oh, didn't know that is the case for H3.. but the User Manual does not seem to mention which registers are accessible only from secure world. Where can I find information about this ?
<mripard>
IIRC it's the SMTA that handles this
<kadamski>
ok, so u-boot could not program SMTA to protect those memory regions, right ?
<jelle>
btw does anyone know if there is more information about the h3 hdmi specs avaliable?
<mripard>
all those reasons why accesing a device using devmem is a bad idea...
<solarnetone>
hi all. mainline kernel build questions on Stretch system installed with debian installer here, or debian channel?
<solarnetone>
on A10.
<solarnetone>
cubieboard 1 specifically.
<kadamski>
mripard: from User Manual it indeed seems that all regions are secure by default so u-boot may not be doing anything
<solarnetone>
vagrantc how are you old chap?
<vagrantc>
what about your cubieboard1?
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<vagrantc>
solarnetone: heya!
<solarnetone>
:)
<kadamski>
and why would using devmem be a bad idea? for quick and dirty checks it seems perfect to me. What wrong could happen?
<mripard>
what you experience ? :)
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<vagrantc>
solarnetone: do you need access to nand? that's the main thing i don't have working with the cubieboard1 with mainline linux/u-boot
<solarnetone>
ok, so i need the SPI interface to work. the dts is right in the debian kernel, but spi-sun4i.ko needs to be statically compiled, and spi-dev needs to be a module. the reverse is currently the case. i built a new kernel, using the packaged config: config.armhf_none_armmp, then 'menuconfig'ing the above modifications.
<vagrantc>
cuz, sunxi nand
<solarnetone>
yep, i gave up on nand long ago. even with sunxi drivers, it likes to glitch.
<solarnetone>
i just put a ssd on the sata port, and called it a day.
<kadamski>
anyways, if I understand correctly, be default almost all modules are configured as secure. CCU, RTC, PRCM, USB Host0, GPIO, etc
<kadamski>
and surly I can access at least some of them.. like CCU or GPIO
<solarnetone>
i am confused as to the build process here. i did make all, make modules_install, make install.
<solarnetone>
the new kernel, however, is not booted. the old one is. iirc, there is no specific call in uboot to a kernel version... should be loading vmlinuz, unless i am confused.
<kadamski>
yet, I can't find where u-boot might configure those so they should stay as default
<solarnetone>
i asked you cause debian installer and all... there is something i am missing.
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<nove>
if anyone remembers, some time ago, i talked about a dubious tracer based in qemu, after lots of laziness this is what is done http://repo.or.cz/qemu/dtv.git
<nove>
there are some features still to do like, include console output, look what can be done with ftrace to show a calltree (function entry/exit), maybe track memory allocation