Turl changed the topic of #linux-sunxi to: Allwinner/sunxi /development discussion - did you try looking at our wiki? https://linux-sunxi.org - Don't ask to ask. Just ask and wait! - https://github.com/linux-sunxi/ - Logs at http://irclog.whitequark.org/linux-sunxi
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<MoeIcenowy> jernej: it solved a problem far serious than this
<MoeIcenowy> for the single-rank problem it's solved in v2
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<MoeIcenowy> jernej: model B U-Boot HDMI solved
<MoeIcenowy> it's because of HDMI DDC_EN pin
<MoeIcenowy> (PH2)
<wens> lol
<MoeIcenowy> wens: how to model it?
<MoeIcenowy> it's a gate independent of SoC
<wens> is it a pull-up for DDC, or the 5v over HDMI?
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<wens> MoeIcenowy: what board is this?
<wens> OK. I see, it's for the voltage conversion
<MoeIcenowy> yes
<wens> MoeIcenowy: you could model it as an i2c-gate, with a regulator supply, under the i2c-bus, though that is overly complex
<MoeIcenowy> but there's no binding for this i2c-bus
<MoeIcenowy> as it's internal
<wens> probably just a supply for the hdmi node
<MoeIcenowy> it's just a GPIO
<wens> which controls a signal level converter
<wens> I don't think there's a binding for level converters though
<MoeIcenowy> or a generic GPIO gate?
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<anarsoul> mripard: hey
<anarsoul> mripard: so can you try some dcs read commands on your board with dsi panel? e.g. read power state?
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<MoeIcenowy> jernej: but Linux HDMI still doesn't work
<anarsoul> reading power state doesn't for on my panel on bsp driver...
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<anarsoul> hm, I tried the other way - I tried to use mainline reg values for tcon and dsi on bsp
<anarsoul> and it's pretty hard to break it
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<anarsoul> it still outputs some kind of image, distorted of course
<anarsoul> also I removed 'init' sequence from lcd panel driver and it still works, so I guess it doesn't need it
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<anarsoul> found another bug in clock driver
<anarsoul> *sigh*
<KotCzarny> good job! get them tiger!
<KotCzarny> :)
<anarsoul> driver sets mipi_dsi_clk_reg to 0x8001
<anarsoul> well, however maybe I'm wrong...
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<anarsoul> if I change it to 0x8002 I get different pattern on LCD
<anarsoul> I thought it's distorted white since I'm using white test pattern
<anarsoul> but apparently it's not
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<anarsoul> so my guess is that dsi is sending something to panel
<anarsoul> but tcon doesn't send anything to dsi
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<lvrp16_> what do you guys use for ddx in x11?
<MoeIcenowy> modesettings when no mali blob
<MoeIcenowy> or armsoc (forced by mali blob)
<wens> new dmabuf blob still requires armsoc?
<lvrp16_> which armsoc branch do you use?
<lvrp16_> yeah that is what i'm wondering too
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<lvrp16_> in so far as i know, the dma buf hasn't worked for me
<lvrp16_> x11 crashes as soon as i try to run es2gears_x11
<KotCzarny> wrong blob maybe? (just a guess)
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<MoeIcenowy> lvrp16_: patched mripard's
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<lvrp16_> any more patches i should throw on top?
<MoeIcenowy> I dropped hardware cursor
<MoeIcenowy> for early DE2
<lvrp16_> KotCzarny: all the other blobs just say "failed to initialize EGL display"
<anarsoul> finally :) I got it working
<anarsoul> timings are a bit off, but it's fixable
<anarsoul> and tcon driver doesn't report vblank properly if dsi is used
<anarsoul> bsp driver uses dsi interrupt for that
<anarsoul> so I'll need to hook it up
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<mripard> anarsoul: great :)
<mripard> (sorry, I just saw your message)
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<anarsoul> mripard: I still have few problems though
<anarsoul> AVDD regulator supplies several consumers
<anarsoul> so linux may enable AVDD before DVDD
<anarsoul> panel doesn't like it, axp overheats and board shuts down
<anarsoul> (AVDD is DC1SW, it also powers ethernet PHY on pine64)
<anarsoul> another problem - I need to read tcon_div from DSI driver
<anarsoul> and I'm not sure how to properly do that
<mripard> why?
<anarsoul> mripard: I need it to calculate SUN6I_DSI_BURST_DRQ_REG value
<mripard> (and I'm not sure there's something in the regulator API at the moment to deal with that)
<mripard> do you just need the divider?
<anarsoul> yes
<mripard> then you can do it pretty easily by using the TCON clock rate and its parent
<anarsoul> so I need to pass tcon0 clock to dsi driver via dts?
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<rellla> mripard, do you have any clue about the deinterlacer on the various socs? afaics on the newer ones (H3, H5...) it's separated from the display engine/ scaler.
<rellla> and on the older ones it's part of the scaler?
<MoeIcenowy> jernej: interestingly... in U-Boot it works but in Linux it doesn't
<MoeIcenowy> (Pine H64 model B HDMI
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<mripard> anarsoul: you can call clk_get_parent I think?
<mripard> rellla: any clue about what?
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<rellla> mripard: about if it is correct, what is said above.
<MoeIcenowy> mripard: what's the current status of Request API?
<rellla> meaning, implementing a deinterlacer for A10/A20 -> use drm, for H3/H5 -> do a separate v4l2 driver?
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<mripard> rellla: I haven't been able to find any info about a deinterlacer on the H3, where did you find it ?
<mripard> MoeIcenowy: likely to be merged in 4.20
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<pgreco> mripard, I didn't see R40/V40 listed anywhere in the cedrus news
<pgreco> any hardware difference I'm not seeing, or just wasn't tested?
<pgreco> MoeIcenowy: I was thinking about using bpi-m2b for a project, but I see that some patches landed for r40 and not for v40 (both kernel and uboot)
<pgreco> patches related to the common things
<pgreco> do you have have a device to test until I get mine? if I bring the dts to the same level as r40?
<MoeIcenowy> pgreco: I have a BPi M2B
<MoeIcenowy> and you should know that R40 display is just supported yet
<pgreco> MoeIcenowy, that is one of the thinks I was talking about
<pgreco> also gmac on uboot landed a few days ago for r40 (and not for v40)
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<rellla> Makefile says, it's build for H3, H5, H6, A64 and a few others ...
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<pgreco> MoeIcenowy, I was thinking about something like this https://paste.fedoraproject.org/paste/hBRg5QrwrmhUn1L~ZdTjAQ/
<pgreco> also mmc definition is out of order in the m2b
<pgreco> and some things can be renamed to fully match m2u
<pgreco> iiuc, the only real difference between m2u and m2b is the extra mmc and 1G vs 2G RAM
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<g8world> shell
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<mripard> pgreco: it wasn't part of the list of SoCs we intended to support in our first release, but it shouldn't be that different
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<jernej> MoeIcenowy: Without schematic and actual HW I can't really comment...
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<MoeIcenowy> jernej: unfortunately schematic has the same thing with model A at HDMI
<MoeIcenowy> except for DDC_EN, which I fixed this afternoon
<pgreco> MoeIcenowy, if the patch looks ok, I was thinking about unifying both devices, and only adding mmc2 to the m2u
<MoeIcenowy> they have also difference at USB
<MoeIcenowy> but maybe they're worth unifying
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<pgreco> if that looks ok, I can do a 2 patch series, 1 sync, 2 unify
<pgreco> btw, that is just a theory, completely untested :)
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<MoeIcenowy> I'm doing
<MoeIcenowy> no need for a common
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<MoeIcenowy> jernej: last linux-next with 12/18 and 13/18 applied cannot display on BPi M2 Berry (with M2 Ultra DTB)
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<MoeIcenowy> oh sorry it works
<MoeIcenowy> just I didn't enable VC...
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<pgreco> MoeIcenowy, nice!!!, I didn't know how to /delete-node/
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<pgreco> MoeIcenowy, can you do the same for uboot?
<MoeIcenowy> jernej: yes it has some problem... it failed to drive my father's 1920x1200 DVI monitor
<MoeIcenowy> pgreco: for u-boot I cannot do
<MoeIcenowy> BTW you can always just use ultra image on berry
<pgreco> and kernel will choose the right dtb?
<pgreco> or will it try to use the ultra one?
<MoeIcenowy> ultra dtb also works on berry
<MoeIcenowy> the extra LED on ultra is NC on berry
<MoeIcenowy> usb1 is enabled both on ultra and berry, and usb2 is NC on berry
<MoeIcenowy> mmc2 is NC on berry
<MoeIcenowy> both usb and mmc is auto probable
<pgreco> thanks
<anarsoul|2> mripard: are you around?
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<MoeIcenowy> KotCzarny: I have a Sunvell R69 with the former owner wrongly written a SB key to it
<MoeIcenowy> what should I do on the box?
<anarsoul|2> jernej: or you?
<KotCzarny> sb key?
<MoeIcenowy> KotCzarny: secure boot key
<MoeIcenowy> you know H3 supports it
<anarsoul|2> MoeIcenowy: you're definitely around :)
<MoeIcenowy> and he flashed some Chinese AliOS
<KotCzarny> ahm, i think you know better in such case
<MoeIcenowy> yes
<MoeIcenowy> now it can only boot via FEL
<anarsoul|2> MoeIcenowy: how familiar are you with sun4i drm driver?
<KotCzarny> there was a way to still boot if it wasnt entirely locked write
<MoeIcenowy> KotCzarny: it is
<MoeIcenowy> anarsoul: so unfamiliar
<MoeIcenowy> but maybe you can ask
<MoeIcenowy> I think the log collector of mripard and jernej are all here
<MoeIcenowy> if their persons are not
<anarsoul|2> MoeIcenowy: mripard: jernej: so I need to plug DSI vblank interrupt somehow into tcon driver
<KotCzarny> then unless you manage to crack the key then write your own proper uboot, there is nothing to do i'm afraid
<anarsoul|2> I'm going to split tcon irq handler into common part and into tcon-specific part
<MoeIcenowy> KotCzarny: yes so it entered a "鸡肋" state
<anarsoul|2> and export global part
<MoeIcenowy> anarsoul: maybe we should refactor vblank code
<MoeIcenowy> not tcon int code
<anarsoul|2> is it a right way?
<anarsoul|2> MoeIcenowy: as far as I understand it's all in tcon irq handler
<KotCzarny> that chinese chars translate to 'chicken rib'
<KotCzarny> *those
<MoeIcenowy> KotCzarny: it's a phrase
<MoeIcenowy> which means "not so useful, but not willing to drop"
<MoeIcenowy> or the original text "食之无味弃之可惜"
<KotCzarny> you can try rooting the droid, then playing around then
<MoeIcenowy> the droid is dropped...
<MoeIcenowy> and now the only boot method is FEL sideload
<KotCzarny> does it still boot that way?
<KotCzarny> or brom refuses to load unsigned loader?
<MoeIcenowy> yes, I can sideload a SPL and then U-Boot etc via FEL
<MoeIcenowy> FEL doesn't load any loader
<MoeIcenowy> it only load words
<KotCzarny> nice to know that
<MoeIcenowy> anarsoul: yes
<MoeIcenowy> you should split it to two functions
<KotCzarny> it means one can still work on such box
<MoeIcenowy> one dealing with vblank
<anarsoul|2> MoeIcenowy: that's what I was going to do
<MoeIcenowy> one dealing with TCON irq
<MoeIcenowy> KotCzarny: I used to use it to test the behavior of secure H3
<KotCzarny> btw. those previous chinese chars translate to: "It's a pity to eat without taste"
<MoeIcenowy> but now I have a burned BPi M2 Zero early sample
<anarsoul|2> just need to figure out how to get pointer to tcon in dsi driver :)
<KotCzarny> also, it means one can probably buy those alios victims cheaply
<MoeIcenowy> KotCzarny: to be honest I "bought" the victim for free
<KotCzarny> :)
<MoeIcenowy> only shipment fee for <$2
<KotCzarny> nice
<MoeIcenowy> I think I need some sunxi-feld to boot locked devices up
<MoeIcenowy> ;-)
<anarsoul|2> btw, DE and HDMI patches for A64 haven't landed yet, have they?
<KotCzarny> yeah, and some cheap usb capable device in a convenient stick format
<MoeIcenowy> KotCzarny: maybe I should try use CH554?
<MoeIcenowy> (a cheap 8051-based USB MCU
<paulk-leonov> anarsoul|2, on h3 DSI uses 8080 CPU mode for vblank interrupt IIRC
<paulk-leonov> on A33*
<paulk-leonov> sorry
<MoeIcenowy> paulk: so from TCON view they're diferent?
<anarsoul|2> paulk-leonov: it's enabled, but it's not signalled here
<anarsoul|2> paulk-leonov: and BSP driver uses DSI interrupt for vblank on A64
<paulk-leonov> anarsoul|2, heh I have the same problem with a DSI panel on A33, I'm not getting the vblank interrupt
<KotCzarny> MoeIcenowy: but honestly, other than experimentation device, r69 isnt particularly interesting (needs a fan to work reliably, and it's h2+)
<paulk-leonov> so it just hangs until it timesout
<MoeIcenowy> it comes with a HS
<anarsoul|2> paulk-leonov: how did you fix it?
<MoeIcenowy> KotCzarny: so maybe I can drop it
<KotCzarny> HS ?
<paulk-leonov> anarsoul|2, I didn't, it's still broken at the moment
<MoeIcenowy> or gift it to another one?
<MoeIcenowy> heatsink
<KotCzarny> ahm, still, needs fan
<anarsoul|2> paulk-leonov: I see :) so I guess you can try my patch when it's ready
<KotCzarny> heatsink alone isnt enough
<paulk-leonov> anarsoul|2, for sure!
<KotCzarny> keep it for SB experiments or send to someone who is interested in hacking secureboot
<MoeIcenowy> KotCzarny: I have another SB device
<MoeIcenowy> (without key
<MoeIcenowy> and as a SBC it can have more usage (e.g. attach a JTAG to dump S-BROM
<anarsoul|2> paulk-leonov: btw, do you have patches for DSI on A33?
<MoeIcenowy> paulk-leonov: this problem happen only on a panel or on all panels?
<paulk-leonov> anarsoul|2, not really, I haven't modified the driver much, just added lots of debug
<anarsoul|2> paulk-leonov: I see
<paulk-leonov> I think timings calculation might be wrong in a few places
<paulk-leonov> MoeIcenowy, mripard has a panel that works for sure
<paulk-leonov> but apparently it's the only one known to work
<paulk-leonov> with the mainline driver
<MoeIcenowy> ahhhhhhhhhhhhh
<anarsoul|2> paulk-leonov: well, timings are wrong for sure for me
<anarsoul|2> but I know where to fix it
<paulk-leonov> since it's an android tablet I'm working on, I can just dump register from Android, where it works
<anarsoul|2> paulk-leonov: I have BSP driver code
<paulk-leonov> yes me too
<anarsoul|2> anyway, https://github.com/anarsoul/linux-2.6/tree/sunxi64-4.17-dsi if you need some inspiration :)
<anarsoul|2> I have one more pll-mipi fix not pushed
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<anarsoul|2> looks like it doesn't work when it's freq < 300 MHz
<anarsoul|2> it does work on 330MHz, but doesn't on ~290MHz (don't remember exact value)
<anarsoul|2> I had to use my pinebook to figure that out
<anarsoul|2> i.e. I removed all parent but pll-mipi for tcon0
<anarsoul|2> disabled video init in u-boot to make sure that everything works from scratch in linux
<anarsoul|2> and started trying to get it working
<paulk-leonov> I see
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<jernej> anarsoul|2: I suggest you take a look at BSP for minimal acceptable clock rate since datasheets tend to be unreliable about that (at least for H3)
<anarsoul|2> jernej: I couldn't find minimal rate for it in BSP driver
<jernej> let me check
<anarsoul|2> anyway, it's pretty confusing - reg says that PLL is locked, but display shows nothing
<jernej> which pll? mipi?
<anarsoul|2> yes
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<jernej> ah, there is only maximum, 1440 MHz
<jernej> but I guess you already check BSP algorithm for calculating PLL MIPI factors
<anarsoul|2> jernej: well, mainline driver calculates factors correctly
<anarsoul|2> the problem is that it doesn't work at ~290 MHz
<jernej> I know that PLL CPU was rather picky about some factors
<anarsoul|2> and datasheet says that pll mipi must be in 500MHz - 1.4GHz range
<anarsoul|2> yet, BSP driver sets 330 MHz
<willmore> Is there a post divider?
<anarsoul|2> willmore: no, there's pre-divider (M)
<willmore> That's odd, then. Most PLLs have an inherent /2 to square up the signal and often generalize that to a divide by N.
<MoeIcenowy> jernej: sorry for bothering for 1920x1200 support on R40
<MoeIcenowy> R40 just doesn't claim it
<MoeIcenowy> but maybe we need a smaller dclk range for R40?
<anarsoul|2> willmore: pll_mipi = (pll_video0 * n * k) / m
<anarsoul|2> willmore: k >= 2, m / n <= 3
<anarsoul|2> pll_video0 / m >= 24 MHz
<jernej> MoeIcenowy: I suggest you first enable drm.debug and check edid info
<MoeIcenowy> jernej: `Modeline 40:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9`
<willmore> anarsoul|2, thanks. I'll peak at it.
<jernej> could you show me clk_summary with display connected?
<anarsoul|2> jernej: do you know what's the status for upstreaming A64 HDMI?
<jernej> yes, it's still wip
<willmore> Is pll_video0 fixed or determined by something else programatically?
<anarsoul|2> willmore: scroll up and check pll_video0 :)
<willmore> k
<anarsoul|2> IIRC it's at offset 0x4 or 0x8 - somewhere at the very beginning of reg block
<MoeIcenowy> anarsoul: it's near final, but we need to wait for Jagan
<willmore> anarsoul|2, that's a pretty complex clock tree there...
<MoeIcenowy> jernej: strangely tcon-tv0 is still 297MHz
<anarsoul|2> willmore: yep
<anarsoul|2> willmore: pll-video0 is usually 297MHz
<willmore> anarsoul|2, so, with pll-video0 at 297MHz, you want <300MH out of pll-mipi?
<jernej> MoeIcenowy: good luck with debugging clocks :)
<MoeIcenowy> jernej: oh the hpd is also not stable
<MoeIcenowy> it can have "[CONNECTOR:38:HDMI-A-1] status updated from disconnected to disconnected"
<anarsoul|2> willmore: why not?
<anarsoul|2> pll-mipi input is divided by M
<jernej> MoeIcenowy: yes, that's known
<jernej> HW issue
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<MoeIcenowy> when inserting the WaveShare 1024x600 screen
<MoeIcenowy> tcon-tv0 become 32MHz
<MoeIcenowy> so does hdmi
<jernej> that's ok
<MoeIcenowy> (I mean the clock named "hdmi"
<jernej> could you put full clk_summary on pastebin for 1920x1200? I'm really interested what's going on
<MoeIcenowy> if it's R40 CCU issue, maybe the one who to blame is myself
<anarsoul|2> jernej: my guess is that it failed to find a divider
<anarsoul|2> for dclk
<MoeIcenowy> also my guess
<MoeIcenowy> do you want the 1024x600 clk_summary?
<MoeIcenowy> maybe it will help
<MoeIcenowy> https://pastebin.aosc.io/paste/I4rm0MBUKfATvIgqWgOVlg here's 1024x600 ws lcd clk tree
<MoeIcenowy> mysteriously after insert-reinsert the ws screen, the clock changed again
<jernej> do you see that for 1920x1200 tcon-tv clock is not enabled?
<MoeIcenowy> jernej: whaaaaaaaaaaaaaaaaa?!
<anarsoul|2> why dotclock isn't here?
<jernej> yes, I noticed that waveshare is not happy with replugs
<jernej> not sure
<jernej> but clocks always consume most of the time to fine tune :)
<MoeIcenowy> BTW the correct dclk of ws lcd is 32MHz
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<MoeIcenowy> (It's interesting to see it work @ 65MHz
<MoeIcenowy> jernej: happy *with* replugs or *without*?
<anarsoul|2> MoeIcenowy: it's probably divided, that why I'm wondering why dotclock isn't in tree
<MoeIcenowy> I think tcon channel1 has no internal divider
<anarsoul|2> MoeIcenowy: with dclk_div = 2 it becomes 32.5
<jernej> usually it worked only when plugged before boot, subsequent replugs worked only in rare cases
<jernej> channel 1 doesn't have predivider
<anarsoul|2> oh
<MoeIcenowy> kernel log for HP ZR24w (the 1920x1200 DVI monitor)
<MoeIcenowy> on which tcon-tv0 not enabled happened
<jernej> if other parameters are set correctly, higher pixel clocks means just more fps
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<MoeIcenowy> jernej: BTW what will lead to "PHY PLL failed to lock" on DW HDMI PHY?
<MoeIcenowy> (asking for H6
<jernej> that message it's part of general DW HDMI driver, which I received during development, but I forgot how I avoided it
<MoeIcenowy> now on Pine H64 model B I can make U-Boot to display
<MoeIcenowy> but not Linux
<jernej> as I said, no idea
<anarsoul|2> IIRC u-boot was using different clocks than linux
<anarsoul|2> try using another tcon parent?
<jernej> main difference is table for some HDMI settings
<paulk-leonov> jernej, by the way, are you aware of HDMI CEC support status?
<jernej> should work
<paulk-leonov> I think it usually requires binding a device-specific pin, is it also like that on sunxi?
<paulk-leonov> and does it use the media framework or only drm?
<jernej> you need both parts
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<jernej> drm sets it up but media manages it
<jernej> you have to enable DW HDMI CEC support in kernel to have it
<paulk-leonov> oh I see
<paulk-leonov> jernej, and no device-specific binding?
<jernej> you mean in DT? no
<MoeIcenowy> jernej: maybe I should try to use video-equipped U-Boot to boot video-equipped Linux?
<MoeIcenowy> (I now use U-Boot without video, to debug Linux
<jernej> no, that definetly should not be requirement
<jernej> especially for R40, since there is no video support for U-Boot
<MoeIcenowy> I used to did a ugly ver of R40 video
<MoeIcenowy> in U-Boot
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<MoeIcenowy> jernej: (R40) clk_set_rate is not called
<MoeIcenowy> mysterious
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<willmore> anarsoul|2, Okay, looking at the datasheet some more, what are you needing the clock to be <300MHz for? Driving a display at a lower resolution? Then I assume you're using that to clock the TCONx. TCON0 at least, seems to have some further divisors in there.
<willmore> Table 6.2.5.1?
<willmore> No, sorry, 6.2.5.11
<willmore> 6.2.5.9 seems to have some division as well. I don't understand the clocking for all of that, so I can't really dig in much more.
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<anarsoul|2> willmore: that's what driver tcon driver chooses
<anarsoul|2> willmore: basically it selects ~290MHz and tcon_div = 4 to get 72.5MHz for dot clock
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<miasma> hm, interesting decision :-/ https://github.com/Fourdee/DietPi/issues/1550 "We will not support a device which lacks a good standard build quality, and, basic level of software support from the manufacture."
<miasma> apparently they require official vendor support, relatively good mainline support isn't enough
<anarsoul|3> :)
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<willmore> miasma, guess that rules out Rpi
<willmore> anarsoul|3, any reason not to crank it up to 362.5 and a tcon_div of 5?
<anarsoul|3> willmore: nope, but driver doesn't do it
<willmore> The driver doesn't have a concept of a minimum input clock speed? Or are you saying 4 is the max divider?
<anarsoul|3> willmore: are you talking about clock driver or tcon driver?
<willmore> tcon
<anarsoul|3> I can set minimum clock for pll-mipi, and that's what I'm going to do
<willmore> Okay.
<willmore> Then the tcon will pick a sane value over that?
<anarsoul|3> tcon just tries all possible combinations and chooses one that has smallest error
<willmore> Ahh, okay. Then it just needs one more sanity check on its choices.
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<miasma> willmore: dunno. i just noticed that dietpi didn't provide the images anymore. i think we used them in some project
<willmore> I assume dietpi is some stripped down distro? I'm not familiar with it.
<miasma> something like that
<willmore> Do they actually build for a modern processor? ;)
<miasma> i'm not that familiar with that. i think the main reason i heard about was that it had a pretty large selection of board support some time ago
<miasma> but now they've decided that orange pi boards are not worth supporting ¯\_(ツ)_/¯
<willmore> Armbian works for me. :)
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