rellla changed the topic of #linux-sunxi to: Allwinner/sunxi /development discussion - did you try looking at our wiki? https://linux-sunxi.org - Don't ask to ask. Just ask and wait! - https://github.com/linux-sunxi/ - Logs at http://irclog.whitequark.org/linux-sunxi - *only registered users can talk*
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<avph> so the h3/h2+ has 3 sram region (A1 64K, A2 32K and C 44K). Can firmware use any of these without initialisation?
<KotCzarny> yes
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<Mangy_Dog> wow
<megi> SIMs are fun, I remember people making emulated SIMs with PICs to get multiple numbers into a phone
<KotCzarny> nah, this one is about sim toolkit in practically every sim card on the earth
<KotCzarny> and the vulnerability of such
<megi> well, is it though? I still have to ask my provider
<KotCzarny> yup
<KotCzarny> i suspect you would have to ask r&d folks, otherwise no one will know what you are talking about
<megi> my provider is small and very technical, I'm sure they'll know
<megi> whoever thought of running Java on a sim card?
<ynezz> Rust wasn't available 20 years ago
<ynezz> is there anyone with the R40 device who can confirm, that watchdog is working as expected with 4.19.y kernel?
<KotCzarny> megi: in such case, yeah, would be sensible to inform them of such vuln
<megi> well, fine, but why not instead use that space to give me more than 50 sms storage, or whatever it was
<KotCzarny> you think about contacts
<KotCzarny> :)
<megi> sms are limited too
<KotCzarny> in the old days they limited it to ~100 contacts per sim
<megi> yeah, contact limits are even stupider
<KotCzarny> memory was short
<KotCzarny> be happy it was 100 not 10
<megi> not so short to cram the sim toolkit there
<megi> and it's there on the current cards still
<KotCzarny> and it wont go away, no worries.
<megi> :D
<megi> btw, I've written DMA support for u-boot/sunxi-mmc
<megi> and fixed some bugs, and now I get 47MiB/s load speed from eMMC during kernel load :)
<megi> faaaast booting
<megi> it looks like that at least back to H3, all the SoCs have new timing modes for sdio controller, including H5, which has it by default
<fALSO> yo
<megi> and need doubling the SD controller clocks
<sunshavi> megi: which one was the previous speed?
<megi> it all just incidentally hangs together on some SoCs because mainline u-boot/kernel thinks the parent clock is half the speed
<megi> 5MiB/s
<megi> but there was another issue there with bus width
<sunshavi> mmm. That's a great improvement. Should I try It on my opi+2e?
<megi> I've also added support for MMC_DDR52 to u-boot, so it can be as fast as the kernel
<megi> normally it should work around 10-20MiB/s, depending on the SoC
<megi> On H6 it was 10MiB/s
<sunshavi> from 5 MiB/s to 10 MiB/s (it would be the double on worst case)
<megi> 5MiB/s was just on one tablet which had mis-configured SD bus width
<sunshavi> :o
<megi> you can try picking up patches from here, if you like https://megous.com/git/u-boot/log/?h=opi-v2019.10
<megi> it's those few latest mmc ones
<megi> i've only checked on H3,H5,H6 and A83T
<megi> I don't have anything else
<sunshavi> i just have H3 :)
<megi> it will not work on older A's, because those have more limited block size
<megi> for dma
<megi> there's DMA_BUF_MAX_SIZE macro that's need to be changed for those to work
<KotCzarny> uboot speed isnt that important, unless one is loading multi MB ramdisks
<KotCzarny> still nice
<megi> I'm planning to use this for pinephone to get past the u-boot very fast to the running kernel
<megi> if I ever get my hands on one
<avph> megi: nice, is it also used by the SPL?
<megi> it could, but that uses different code paths for initialization
<megi> so more code chnages would be needed
<megi> and I'm not sure if SPL can allocate memory in DRAM
<megi> or what malloc in SPL will do
<megi> but you can probably get away with allocating just 10-20 DMA descriptors for the main u-boot to load from emmc so it may not be that memory hungry
<megi> at least on newer socs
<megi> anyway I specifically disabled this for SPL for now
<megi> and if someones wants some other fun patches to try, I've made these two drm patches https://megous.com/git/linux/log/?h=private-5.3 to enable Xserver to use "HW" cursor
<megi> makes desktop use somewhat more smoother
<fALSO> ;-)
<fALSO> i have to try it
<megi> especially if you move a mouse a lot :D
<fALSO> but i was never able to clone your repos
<fALSO> from your server
<fALSO> it timeouts or something, always exits with error
<KotCzarny> megi, use arisc to draw mouse pointer? :>
<megi> you can try again, I fixed that
<fALSO> nice, i also now learned about
<fALSO> --depth 1
<fALSO> LOL
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<megi> git clone https://megous.com/git/linux ;)
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<fALSO> i have to try it again
<fALSO> i have your kernel being built on my jenkins
<fALSO> when theres a new commit
<fALSO> but im using your github mirror
<megi> oh :)
<fALSO> SOON(tm) ill change it
<fALSO> and waste your BW
<fALSO> :-PPPPPPPPPPPPppppppppppppppppp
<megi> well, you may be surprised :)
<fALSO> hehehe
<megi> that clone command will end very quickly
<fALSO> im also using a gitea...
<fALSO> you are using a cgit i think
<fALSO> or were
<megi> yes
<fALSO> i didnt install that one because emailing PR is hard :-P
<fALSO> i prefer to do clicks
<fALSO> hehehe
<megi> I like the speed of cgit
<megi> even without cache it's blazing fast
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<fALSO> yap
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<willmore> KotCzarny, that vulnerability is as bad as they portray it to be. Your provider can send SMS messages that your phone will silently receive and pass to the SIM. These messages can install applications that run on the SIM itself--completely out of sight of the phone. Those applications have access to a lot of information and can also silently send SMS messages that the UI of the phone will not say anything about.
* willmore used to work in cell phone provisioning for what is a large provider in the US.
<fALSO> from what i've talked with a portuguese cell phone company
<fALSO> we arent using that vuln here in portugal
<fALSO> so they say
<fALSO> "trust jesus - dont think" :-)
<mru> they would say that
<fALSO> let me check what they've said
<mru> willmore: is there any way to tell if your sim has such features?
<fALSO> they told that they dont use S@T
<fALSO> whatever that is
<mru> _they_ don't use it
<fALSO> GSM sucks
<fALSO> should be disabled 10 or more years ago
<willmore> It's in the SIMs themselves. They're already using the functionality if they can provision a SIM without removing it from your phone.
<mru> doesn't mean the sim doesn't have the feature
<fALSO> GSM has tons of bugs
<fALSO> uses crappy voice compression
<willmore> mru pretty much all SIMs have it.
<fALSO> i dont understand why we keep using that old technology
<fALSO> with top of the line mobile phones
<fALSO> its very weird for me :-)
<mru> modern phones with 3g/4g support better codecs
<willmore> the voice codec in GSM is very good, I'm not sure what you're thinking of fALSO
<fALSO> well, the quality in voice calls is ultra crappy
<fALSO> at least in portugal
<willmore> The original one was okay, but the EFR codec that was released in the late 90's is very good.
<willmore> If your landlines are bad, the cell phone won't make it better.
<fALSO> released in the 90s? isnt that too soon for they to be using it ;-PPPPPPPPP
<willmore> IIRC, it was mandated as baseline in the 3g specs.
* willmore worked on EFR support at Motorola
<fALSO> nice
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<willmore> wens, looks like my Orange Pi One Plus is taking a long time on boot before the ssh daemon is running as I'm getting network responses from it, but ssh fails to connect. So it sounds like it's the issue libv was talking about. I'll hook up a serial line to it to verify.
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<KotCzarny> willmore: yeah, i know, sims are tiny computers itselves, with ability to control your phone. that's why it's dangerous
<KotCzarny> as for boot time, other apps might wait for random device too
<KotCzarny> it's not only tied to sshd
<KotCzarny> if you install haveged and it helps, that will be it
<KotCzarny> but might lower randomness quality
<willmore> Thanks, KotCzarny.
<KotCzarny> ugly pastebin. doesnt work without js
* KotCzarny barfs
<willmore> I'm okay with it taking a while to come up, I just wanted to make sure I knew why it was doing it--and it wasn't because of something going wrong.
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<avph> Does the H2+ BROM have a gpio to enter FEL mode? BTW is the BROM the same for all SOC variants or is that something vendors can modify?
<Mangy_Dog> The AP6212A wifi/bt module on most of these boards.... Is there an example circuit diagram of how to hook one of these up? And to what ports on a SBC/CPU to wire them to? If i was to use a Compute Module type setup?
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<karlp> have you tried looking at tje available schematics of those boards?
<hellsenberg> avph: I found some orange pi zero (your board) "schanetic" (schematic, but filename says that). let me see if I can find a link
<KotCzarny> the usual, but at least its available
<KotCzarny> avph: treat h2+ as h3
<KotCzarny> they are virtually the same
<KotCzarny> and brom is embedded in chip by allwinner, the only thing that vendors customize is efuse (sid)
<KotCzarny> and often not even that
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<hellsenberg> KotCzarny: is there any important difference between h2+ and h3, or are they the same silicon die with more or less disabled blocks?
<avph> KotCzarny: so what GPIO enables FEL?
<avph> *pin
<hellsenberg> avph: I can see this: https://linux-sunxi.org/Orange_Pi_Zero#FEL_Mode
<hellsenberg> if you want to use fel for reflashing the spi, i guess you could just put the flash chip on hold and boot, then once in fel enable it again
<avph> looks like the FEL pin is strapped to VCC via a 47K resistor. Might be doable to add a switch to ground
<hellsenberg> which pin is that?
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<avph> W6
<hellsenberg> ah, UBOOT. thx
<hellsenberg> now then, where's that R124...
<Mangy_Dog> ohh schematics
<Mangy_Dog> thats useful :D
* hellsenberg prefers boardviews but those are more usual on x86 things
<Mangy_Dog> well it does explain a little for me of how the wifi works
<Mangy_Dog> its just i might be doing a pi4 compute module version of my game machine
<Mangy_Dog> (if the rumours about a pi4 Cm are true)
<Mangy_Dog> and i just watned to have a quick look to see how the wifi chip would need to be wired up
<Mangy_Dog> So i knew what to look out for on the CM pin out
<hellsenberg> rpi "schematics" more like pinout
<Mangy_Dog> nods
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<mru> Mangy_Dog: cubietech provide schematics for some boards using ap62xx wifi modules
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<megi> looks like sunxi u-boot has useless 500ms fixed delay on many boards
<Mangy_Dog> is it possible to configure uboot to work with a soft power button? So as soon as power is turned on the mcu and cpu start up.... Within a few MS a GPIO on the SBC is set to pull to ground. Keeping the soft power engaged... And when shutdown commands are sent by the OS uboot kills the IO which powers off the device?
<megi> not sure I understand
<megi> what's the purpose
<megi> ?
<Mangy_Dog> to turn on a device
<Mangy_Dog> and shutdown command actually power off the machine
<megi> u-boot doesn't come into play during shutdown
<megi> you can toggle gpio on shutdown from linux
<[TheBug]> I think the question is can uboot manipulate a gpio to enable a device at boot time, preferably before the OS starts to boot (maybe a display?) and then when you shutdown, it powers off the whole unit so whatever is attached also turns off (display?)
<megi> but you'd need to patch it
<[TheBug]> if I have decoded correctly what he is saying
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<[TheBug]> Mangy_Dog??
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<DuClare> Anyone reverse engineered boot0 dram setup?
<DuClare> Just wondering if there were any resources on that in case I want to go there and not waste too much time re-discovering the wheel :P
<DuClare> I couldn't ever get good dram clocks from mainline u-boot spl so I'm loading u-boot via boot0.. which works but meh, ugly
<libv> DuClare: can you dump the dram registers, and do you have any info on their layout for your specific soc?
<libv> if so, it's as easy as printing out the values from uboot in code or even in command line, but you can pretty print it in code
<anarsoul> DuClare: you should specify SoC, board and ram type
<anarsoul> (LPDDR3 for A64 runs at 552 MHz while it should be running at 667, but unfortunately we don't have correct timings for that... boot0 also uses 552 MHz)
<hellsenberg> anarsoul: which kind of timings are missing?
<anarsoul> hellsenberg: see u-boot/arch/arm/mach-sunxi/dram_timings
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<hellsenberg> anarsoul: I don't think that specifically answers my question. are the only timings in https://github.com/u-boot/u-boot/blob/master/arch/arm/mach-sunxi/dram_timings/lpddr3_stock.c the 552 MHz timings?
<anarsoul> yes
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<DuClare> anarsoul: S3, custom board, DDR3.. I'm running at 672 (IIRC) with boot0
<DuClare> libv: If I understand it right, there are dram control registers in the soc and then some registers in the dram chip itself, right?
<DuClare> Which ones do I need to get to?
<DuClare> I don't remember seeing much info about the dram part in the datasheet
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<DuClare> So there are DRAMCOM, DRAMCTL0, DRAMPHY0
<DuClare> Can't remember if I ever checked the clock source..
<hellsenberg> DuClare: problem is with lpddr3 though
<hellsenberg> do not confuse lpddr3 with ddr3l though
<DuClare> It's not supposed to be lpddr3 on the s3
<hellsenberg> timings are missing on lpddr3
<DuClare> Yea, that's not my issue.. :) There are timings for ddr3 but they're no good for the clocks I'm trying to reach, or something else is wonky
<DuClare> 360 MHz (which is the default in u-boot, IIRC) seems stable alright but beyond 408 MHz it's crashfest
<hellsenberg> welp
<libv> sochip s3?
<libv> is this a rebadged allwinner?
<libv> de2.0 display...
<libv> heh, i had no idea
<DuClare> Allwinner s3, sochip s3, same chip afaict
<DuClare> Don't ask why, I don't understand it myself :P
<DuClare> And yeah dram is in the package
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