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<splitice>
megi & MoeIcenowy & smaeul: I am pleased to report success with the patch provided. 6/6 days continuous uptime. Normal MTBF pre-patch of 2.3 days.
<splitice>
For anyone who needs it here is the required elements to add voltage regulation to a NanoPI NEO / Air. https://paste.ee/p/0t1Sr
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<tuxd3v>
sunshavi, Hey, I manage to compile 'libva-v4l2-request' shared library
<sunshavi>
youtube-dl. no way. I only have 16 Gb emmc for all my needs. I only have 1 Gb free.
<aloo_shu>
I have pathetic bandwidth
<sunshavi>
tuxd3v: for today I am going to leave it as it is. I think a good alternative is having all the kernel repo and comparing the file h264-ctrls.h on different kernel versions from 5.3 on until 5.5. That way we could get an idea the moment than struct field was removed, and which field replaced it
<sunshavi>
aloo_shu: then ur main machine is not a pi. or You have an external hdd attached to it
<aloo_shu>
i'm using old tablets. but I'm off gtid, and far ftom mobile antenna
<aloo_shu>
from
<aloo_shu>
think edge
<sunshavi>
tuxd3v: for not seting-up a desktop image. You could try ssh forwarding from an ethenet connection that should work. But i have tested that even today without luck. THat's the reason i have tried to solve it today
<sunshavi>
aloo_shu: gtid?
<aloo_shu>
sry
<aloo_shu>
off grid
<tuxd3v>
sunshavi, yeah that is a option indeed :)
<tuxd3v>
does you knowq the minimum amount of cma that I need to alocate?
<tuxd3v>
I know about 256M
<tuxd3v>
but don't know if 128 is okish :)
<sunshavi>
256 is the one i use. i think that's the minimum
<tuxd3v>
yes 1GB total falls short but its what I have.. :)
<tuxd3v>
what DE are you guys using?
<tuxd3v>
I have been using simpler fluxbox
<tuxd3v>
sunshavi, One option that we have to test it is:
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<curlybracket>
Hello. Is the MIPI DSI driver in 5.6-rc5 supposed to work with A64? When I try to run it, the picture looks right, but vblank interrupts occur only 20 times per second which besides choppy animations occasionally causes the screen to flicker. The dot clock, however, is tuned for 60Hz refresh rate. Has anybody encountered such problem?
<mru>
everything is _supposed_ to work perfectly at all times; too bad it doesn't
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<veremitz>
^ LMAO which alternate reality is that!?
<mru>
are you saying things are intentionally broken?
<veremitz>
unintentionally ..
<mru>
right, so everything is supposed to work but doesn't
<veremitz>
but too frequently, a lack of design and testing means that it might work once ..
<veremitz>
so, technically correct, but very idealistic :)
<curlybracket>
Well, let me rephrase my question: There's only a small number of DSI panels available to buy which fit any of the available A64 devboards. Thus the DSI implementation can only be tested for limited number of cases.
<mru>
I didn't say everything is _expected_ to work
<mru>
it certainly isn't
<veremitz>
yeah .. its a nuance of language .. everything -is- expected to work, usually against better odds ;)
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<curlybracket>
For example, my panel has 2 DSI lanes, but the code was likely tested only with 4-lane panels
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<megi>
well, I'm not sure it works even on PinePhone with 4-lanes
<megi>
if I run a test app, that just does atomic update on each flip, I can measure 36.3FPS
<megi>
it should be more like 60FPS
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<willmore>
Does the A64 have one? I have a Pine64 and a 'scope.
<megi>
trying to match the spec first is probably easier atm
<willmore>
I have H2/H3/H5/H6.
<willmore>
But I don't think any of them have a flat ribbon type of display output like the Rpi do.
<willmore>
I think some of them have camera connections....
<megi>
I'd guess that mipi_dsi is specific to A* socs
<megi>
tablet line
<willmore>
Makes sense.
<willmore>
So, I'm probably good with the A64?
<megi>
yup
<willmore>
Hmmm, I may be able to wire something up if you need measurements taken. It's only a 100MHz scope, though.
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<willmore>
Four channel. 2.5Gs/s.
<willmore>
Not a very fancy device.
<willmore>
Yeesh, even for a 640x480x24x60 pannel with no blanking, etc. you're looking at .442 Gb/s
<willmore>
Yeah, that's going to be beyond my scope.
<megi>
thanks, I'm not going to look into the issue, atm, but success criteria would be that refresh rate would match the expectations, and that's easy to see in SW
<megi>
pixel clock is supposed to be 68MHz
<willmore>
transmission clock would have to be some factor larger than that, right? for 24 bits/pixel, you're going to need a data clock 24/#lanes faster.
<megi>
signals are probably a bit faster on the mipi bus :)
<megi>
I think it will be 4x that
<megi>
that's the tcon0 clock
<megi>
274MHz
<willmore>
What resolution is that for?
<megi>
1440*720
<megi>
and DSI DPHY has 150MHz clock
<megi>
so it may be that too
<megi>
really, I have no idea how this works
<megi>
in A64
* willmore
is trying to read up on DSI, display timing, TDMS, etc.
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<willmore>
guessing the TDMS uses 8 of 10 signaling, so the clock rate will be 10 clocks per byte.