rellla changed the topic of #linux-sunxi to: Allwinner/sunxi /development discussion - did you try looking at our wiki? https://linux-sunxi.org - Don't ask to ask. Just ask and wait! - https://github.com/linux-sunxi/ - Logs at http://irclog.whitequark.org/linux-sunxi - *only registered users can talk*
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<KotCzarny> running two bananas, wondering why ethernet dies after a few second
<KotCzarny> cause? same mac, eh
<KotCzarny> what is the proper way to set the mac? uboot env or just ip command?
<KotCzarny> also seems like dts for bpi-m1+ wasnt updated for dvfs and few other things.. hhmm
<KotCzarny> (diffing with bpi-m1 dts)
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<jernej> KotCzarny: mac is usually set in U-Boot based on SID
<jernej> make sure they're different
<KotCzarny> jernej: yeah, but for some reason i got same mac on both devices
<jernej> hm... IIRC only part of SID is used
<KotCzarny> which i only noticed when booted both at the same time
<jernej> can you check SID on both boards?
<KotCzarny> is it exposed via /sys somewhere?
<KotCzarny> or should i dig out my sid tool
<jernej> I think you can read it via sunxi-fel, for example
<KotCzarny> hmm /sys/bus/nvmem/devices/sunxi-sid0/nvmem
<KotCzarny> but values there are funky
<KotCzarny> on bpim1: 00000000 CC 66 51 16 ? 66 56 48 80 ? 48 48 56 53 ? A3 55 C2 09 .fQ.fVH.HHVS.U..
<KotCzarny> on bpim1+: 00000000 95 66 51 16 | 70 50 49 80 | 48 48 52 52 | 22 D1 81 02 | 00 00 00 00 .fQ.pPI.HHRR"Ñ......
<jernej> ok, so I would say they're different
<jernej> do you have ethernet alias in DT?
<KotCzarny> unlikely, i guess its stock dt
<jernej> well then, U-Boot only generate MAC if ethernet alias is there
<KotCzarny> might be (relatively) old uboot
<jernej> talking about mainline U-Boot, of course
<KotCzarny> yeah
<KotCzarny> U-Boot SPL 2016.09-g45b047e-dirty (Oct 02 2016 - 13:36:52)
<jernej> oh, btw, if you're using two separate dtb files, one for U-Boot and another for Linux, make sure both have ethernet alias
<KotCzarny> uboot has separate and loadable dtbs now?
<jernej> one dtb file is embedded in U-Boot and you can load new dtb if you want before booting kernel from file
<jernej> that's supported as long as I can remember
<KotCzarny> you mean, i can load dtb for uboot in uboot?
<jernej> no
<jernej> for kernel
<KotCzarny> for kernel, yes, i know
<KotCzarny> it was this way since beginning
<jernej> but mac is set right before kernel boot, so ethernet alias needs to be in both of them
<jernej> iirc
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<jernej> it's been a while since I checked mac generator
<KotCzarny> wouldnt kernel use the mac set by uboot without needing an alias?
<jernej> true, but without alias, U-Boot won't generate it
<KotCzarny> but since i'm getting some mac, it's probably generated anyway
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<KotCzarny> darn, and patch for axp209 voltages STILL not in mainline?
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<KotCzarny> now. that is better
<KotCzarny> C: 864, 864 T:41.6 PMU: 0.0C 4.558V AC: 0.000A 0.000V CHG: 0.000A BAT: 0.000A 0.000V VBUS: 0.217A 4.646V
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<jernej> anyone have an idea how to measure RTC RC oscillator frequency? Possibly programmatically?
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<mru> jernej: which chip/board?
<mru> it should be somewhere around 32 kHz
<jernej> I'm talking mostly about 40 nm chips, like H3, H5, A64, etc.
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<jernej> yeah, that's the thing, it's not close enough for HDMI-CEC to work
<mru> no, it's useless
<mru> most boards have an external crystal
<mru> use that
<jernej> if I manually lower divider from 16 to 15, CEC works
<jernej> most H3 boards don't have external crystal
<mru> then don't use them
<jernej> :)
<mru> the rc oscillator is too unstable to be useful
<jernej> it's not not me, it's many LE users :D
<mru> but if you want to measure it, send it to a pin and poke it with a frequency counter
<jernej> I did that, but my, albeit cheap, frequency counter always showed 32 kHz
<jernej> even if changed divider in extremes
<jernej> anyway, it would be nice to somehow compare RTC RC oscillator to timer or hstimer which would allow automatic adjustments
<jernej> but I'm not sure how to do that
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<mru> you'd need a counter for that
<jernej> trusted watchdog could be abused for that (LOSC source, counter, interrupt on match), but that's too hackish
<mru> probably too much jitter in the interrupt handling to be useful too
<jernej> well, 32 kHz is not that fast or precise
<jernej> and in most cases prescaler should be shifted just for one up or down
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<mru> hmm, h3 doesn't have a clock output pin like a20 does
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<jernej> it has - X32KFOUT
<mru> ah, it's a fixed function pin
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<mru> and not connected on any of the h3 boards I have
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<smaeul> jernej: on H6 there is a hardware calibration circuit. on older chips, you have to set the divider manually
<smaeul> the way I do it in crust is to set CPUS to IOSC, and then count HOSC cycles vs IOSC cycles
<smaeul> the AR100 has a built-in timer that counts at whatever speed the CPU clock source runs at
<jernej> smaeul: I know that H6 has calibration mode, but I'm interested in older, 40 nm SoCs
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<jernej> smaeul: so you do some kind of 32768 Hz calibration in Arisc?
<jernej> I mean AR100
<jernej> anyway, that's still of the table for H3
<jernej> s/of/off/
<smaeul> well I don't care about 32768Hz directly. I care about IOSC so I can calculate the divider for R_UART baud rate
<jernej> true, but same thing can be achieved
<smaeul> 25% error is way out of UART spec :)
<jernej> I know that issue very well from work
<jernej> we kept usually in +/- 2% range
<jernej> but they were cortex m4 mcus
<smaeul> jernej: TIMER0/TIMER1 can run from the same "about 32KHz" clock source
<smaeul> for calibration, count the number of 24MHz cycles in a "~32kHz" cycle, then multiply by 32*INTOSC_CLK_PRESCAL to get IOSC frequency
<smaeul> you can average across as many cycles as you need
<jernej> that's interesting, thanks!
<jernej> sadly both timers use same source
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<smaeul> jernej: you mean TMR0_CLK_SRC and TMR1_CLK_SRC aren't independent?
<jernej> oh, I misinterpret diagram
<smaeul> where during boot do you plan to do this calibration?
<jernej> good question, I thought to make it cyclic in Linux due to temperature drift
<jernej> but I'm not sure it's worth it
<jernej> but maybe I should try with U-Boot first
<smaeul> hmm, I could measure temperature effects, but I think random variation might be too large for it to matter
<smaeul> oh, s/multiply/divide/ above
<smaeul> you can reduce the rounding error (and thus the time needed) by setting the divider to 1 before calibration, but only if nothing else is using the clock
<smaeul> the general procedure would be 1) set up both timers 2) start slow timer 3) start fast timer 4) spin until slow timer reaches some value 5) read fast timer 6) do math
<jernej> I know the theory :)
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<smaeul> did some quick testing with the calibration code in crust: http://ix.io/2wkQ if the divider being off by one matters, then temperature correction is needed
<jernej> which frequency is that? RC oscillator is about 16 MHz
<smaeul> jernej: that is the RC oscillator. on every A64 device I have, it's 12-13 MHz
<jernej> smaeul: Are you sure? User manual says it's 16 MHz and currently mainline has it set to 16 MHz too (probably doesn't matter)
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<smaeul> jernej: yes, I'm sure. that's why I mention 25% UART baud error. I originally hardcoded 16MHz, and R_UART didn't work. It works up to (at least) 9600 baud with my calculated frequency
<jernej> interesting
<jernej> where do you have this code in crust?
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<smaeul> https://github.com/crust-firmware/crust/blob/master/drivers/clock/ccu_helpers.c#L20 counter_read() is OSC16M, r_twd_counter_read() is OSC24M
<smaeul> to get more precise values for testing, I changed the shift from 9 to 7, and printed *rate
<smaeul> jernej: here's the exact code I was running https://github.com/smaeul/crust/commit/osc16m-calib
<jernej> thanks!
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