<jernej>
smaeul: I just tested 0x00100000 and 0x00100100 via FEL and writel/readl operations and it always return 0
<jernej>
so I would say there is no SRAM A2
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<bauen1>
yog: not really, but if the 1 year lifetime figure is somewhat accurate that would probably be enough for my usecase
<asdf28>
:->
<bauen1>
jernej: if FEL is not in secure mode read / write to SRAM A2 will result in 0
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<yoq>
jernej: also the first 0x4000 of SRAM A2 used to be sparse SRAM for a interrupt vector table. that layout may have changed if they use a different core for CPUS, better check past the first 16kiB
<yoq>
the H616 datasheet has a single reference to SRAM A2 on page 46 in the system bus tree, fwiw
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<apritzel>
so this SRAM "A2" (or whatever) on the H616 is very weird: First I get nothing from U-Boot (non-secure EL2), which is somewhat good news (is it really secure this time?)
<apritzel>
when I write something from TF-A (in EL3), I see some *patches* of SRAM functionality around that area
<bauen1>
apritzel: iirc the SRAM "A2" is the (almost) the only thing correctly marked as secure
<bauen1>
usually the SPC, SMC and some cpu configuration registers are marked as secure and the DMA is setup correctly
<bauen1>
but the RTC (and possibly other) peripherals aren't necessarily set to secure even though they should be
<apritzel>
bauen1: disregard your understanding of the term "usually" when it comes to Allwinner SoCs
<apritzel>
bauen1: first: SRAM A2 is definitely *not* secure on the A64, H5, unless you burn the secure fuse
<apritzel>
the same applies to all peripherals handled by the SPC, regardless of whether you switch them or they are fixed to secure
<apritzel>
IIRC the H6 is the same in this regard
<apritzel>
the SMC worked in my experiments a while back, though
<bauen1>
apritzel: did you burn the secure fuse on your H616 ?
<apritzel>
surely not!
<apritzel>
it just complicates things, and is not what other people do
<apritzel>
I tend to keep my boards in sync with the vast majority of users out there, so I can do actual testing
<bauen1>
apritzel: yeah, that's what i was thinking, which is also why i'm a bit confused that "A2" wouldn't work from non-secure but (somewhat) work from secure
<apritzel>
bauen1: again: this is AW, abandon all hope. There is little rhythm or rhyme to their designs
<apritzel>
a lot of things tend to be similar to previous SoC, but then they change random things here and there
<bauen1>
well, they do like to copy + paste for their technical manuals lo
<bauen1>
*lol
<apritzel>
the quality of the manuals is not good enough to rely on them
<apritzel>
whenever I read something in there, I always try to verify it on the SoC
<apritzel>
so the pattern I see on the H616 is: writes stick between 0xb0000-0xb1100, and 0xc0000-0xc1100, 0xd0000-0xd1100 and so on, and they are distinct (so not aliased)
<apritzel>
later on it might get patchy, with bursts of 64 bytes RAZ/WI in the middle
<apritzel>
which makes me think this might be some clock issue or general instability under certain conditions
<apritzel>
we have seen that in the past, when the AHB1 clock for SRAM C was too fast, SRAM C couldn't be accessed reliably from the CPU
<apritzel>
need to investigate further after nightfall, the clock setup by boot0 seems also dodgy (AHB1 at 4MHz?)
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<hlauer>
pgreco: sun7i-dwmac 1c50000.ethernet eth0: configuring for phy/rgmii link mode - seems to work with 100M too. No clue at the moment...
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<pgreco>
hlauer: is that with 5.10-rcX?
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<hlauer>
yes - wondering even why it's not phy/rgmii-id, as that should be in the dtb...
<hlauer>
5.10-rc5
<pgreco>
maybe it works in 100 but fails at 1G, seems strange
<pgreco>
do you remember what you had booted when it failed?
<apritzel>
so on RGMII when the PHY negotiated 100Mbit/s, we use a 25MHz clock, not the 125 MHz one for 1GBit/s, right?
<apritzel>
which means timing is much more relaxed on a 100Mbit/s link, so those delay might not matter?
<pgreco>
no idea about the clocks, but something like that is what crossed my mind
<apritzel>
can we force the link down to 100Mbit/s easily in Linux?
<pgreco>
with ethtool
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<apritzel>
right, that was it: ethtool speed 100
<pgreco>
ethtool –s eth0 speed 100 duplex full autoneg off
<apritzel>
might be interesting to see if that at least establishes network connectivity with a mismatching DTB, so people can upgrade their way out
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<pgreco>
trying that here
<pgreco>
apritzel: didn't work :(
<apritzel>
bummer!
<apritzel>
pgreco: thanks for trying
<pgreco>
I tested using bananapi-m2b 5.9.2 , rgmii, setting ethtool -s eth0 speed 100 duplex full autoneg off
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<pgreco>
apritzel: for a "way out" this might help fdtput -t s /boot/dtb-5.9.2-301.el7.armv7hl/sun8i-r40-bananapi-m2-ultra.dtb /soc/ethernet@1c50000 "phy-mode" "rgmii-id"
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<apritzel>
pgreco: yeah, if you find that ;-)
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<pgreco>
yeah, ethtool is easier
<pgreco>
but this is easier than rebuilding a kernel :)
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<apritzel>
pgreco: if a *user* needs to *rebuild* a kernel, something is wrong. I was thinking about "apt-get upgrade".
<pgreco>
yeah, unfortunately, I think we're already there the latest 5.8.x was broken for a lot of devices, and 5.9.x is broken for less, but still broken
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<JohnDoe_71Rus>
do you hear about Allwinner R18 ?
<apritzel>
JohnDoe_71Rus: from all we know it's just a relabelled A64, otherwise identical
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<JohnDoe_71Rus>
just read, it is used in yandex.station
<jernej>
apritzel: I received OPi 02, I'm already investigating DRAM init
<apritzel>
jernej: great!
<jernej>
found one difference, but it must be something more
<[TheBug]>
jernej: does that board have wifi and if so what chipset could you tell me (thanks.)
<jernej>
well, it's complicated :)
<apritzel>
[TheBug]: looks at the pictures in the Wiki, it's apparently a new Allwinner Wifi chip
<[TheBug]>
wondering if its another xradio or not
<jernej>
that's just a rebrand
<jernej>
no, it's not, but it's still obscure
<jernej>
let me dig real company/chip name
<[TheBug]>
k
<[TheBug]>
cool, thanks
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<apritzel>
jernej: be careful with your Opi Lite placeholder DT for the Opi02, the power rails are quite different, with TF-A working it was programming them wrongly
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<jernej>
uh, I should remove that part then
<apritzel>
jernej: I have made a proper DT with the correct regulator settings
<jernej>
great, then I'll use your
<apritzel>
papering over the h616.dtsi part for now (that's work in progress here)
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<apritzel>
jernej: it seems like the AXP305 is fully register compatible with the 805?
<apritzel>
including the chip ID (of course!)
<jernej>
apritzel: I didn't investigate, but it seems so, given that U-Boot report it as 805
<jernej>
I mean boot0
<apritzel>
so I went through all the register bits and compared them
<jernej>
I guess only initial settings are different
<apritzel>
I think not even them ...
<apritzel>
jernej: so your TV box was also using the 305, and had DRAM at DCDCD?
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<jernej>
yes
<pgreco>
apritzel: I've already submitted the m2berry, and was merged for next
<pgreco>
just not picked up for stable yet
<apritzel>
pgreco: ah great, thanks!
<jernej>
[TheBug]: wifi is from Spreadtrum WCN, platform is called marlin3 and it's not supported by mainline
<apritzel>
jernej: there is a pin where you can select the initial voltage for DCDCB, to be 1.2, 1.5 or 1.1V, which smells like LPDDR3/DDR4, DDR3, LPDDR4, respectively
<apritzel>
jernej: but it's not used, and apparently the defaults are not specified for the 305, and are of course wrong in case of the DRAM
<JuniorJPDJ>
I've a10 tablet and enabled simplefb
<JuniorJPDJ>
someone told me I need to use other shit to enable hw acceleration