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<jernej>
JuniorJPDJ: there is only one driver which covers all currently supported SoCs, just be sure to enable all needed features or if in doubt, just enable everything
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<smaeul>
TIL sunxi has a turbo bit. Setting bit 21 of PLL_CTRL_REG0 (`devmem2 0x1f01440 w 0x301013`) will double the OSC24M frequency
<smaeul>
this doubles the APB2 bus frequency (=> UART baud) and the ARM arch timer frequency (=> kernel timekeeping), but appears to have no effect on PLL outputs
<smaeul>
somehow doubling the PHY clock doesn't break USB, and it actually manages to make USB transfers 0.5% faster!
<megi>
heh
<megi>
if it makes PIO 2x faster, I can actually use it for 48MHz sampling of signals from camera for debugging
<jernej>
apritzel: found a big design flaw in H616 - they multiplexed RGMII and HDMI SDA, SCK and CEC signals
<jernej>
so, if you want gigabit ethernet, no EDID
<jernej>
and that's what OPi 02 has
<apritzel>
jernej: not the first of those issues ...
<apritzel>
jernej: but please tell me you are on the pinctrl driver ...
<jernej>
Linux will always boot in 1024x768 if not overriden
<apritzel>
jernej: (because I just finished that)
<jernej>
of course, almost finished :)
<jernej>
ah...
<apritzel>
and I have the .dtsi now compiling
<smaeul>
speaking of big design flaws... there's no NMI input, so you can't use the PMIC power button
<apritzel>
and a plan how to tackle the clocks
<apritzel>
smaeul: at least there is an NMI interrupt to the GIC
<smaeul>
connected to what?
<smaeul>
there's some USB standby thing in the RTC block, but no physical NMI pad
<apritzel>
right, the IRQ pin just goes to a test pad on the OPI Zero2
<apritzel>
smaeul: indeed no NMI pin in the datasheet
<apritzel>
also there are other weird things due to them ripping out the whole R_ (or S_) devices, but then not all of them
<apritzel>
so they still have a PL pin controller, and a "secure" I2C, at the old addresses
<jernej>
apritzel: let me know when you push initial work somewhere
<apritzel>
jernej: yeah, we should coordinate a bit, I guess
<jernej>
apritzel: do you have TF-A already?
<apritzel>
I have it running in DRAM, it boots, and reset and power off work
<apritzel>
haven't tested SMP yet, I guess it just some adjusting
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<apritzel>
and I have a plan how to merge it into the tree without making a mess
<jernej>
so no SRAM A2 for now?
<apritzel>
jernej: I will try to push something tonight
<apritzel>
unfortunately not, it seems
<jernej>
now at least I know why no TV box has gigabit ethernet :)
<apritzel>
I see a bunch of 4K+256byte regions between SRAM C and 1MB
<apritzel>
jernej: ah, wanted to ask you that: so your Tanix also has only 100Mbit?
<jernej>
yes, and T95 too
<apritzel>
I just found a lot of "T95" on eBay, they all have 100Mbit/s
<apritzel>
right
<apritzel>
they are quite cheap for 4GB/64GB
<jernej>
well, I2C is not that big deal, you just route to some other free I2C
<jernej>
but question remains if BSP supports that :)
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<jernej>
CEC is a bigger issue - you need SW implementation, which is a bit tricky, but still doable
<apritzel>
isn't CEC just I2C in disguise?
<jernej>
no, it's weird one wire protocol at 32 kHz
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<apritzel>
I see, Wikipedia has list of similarities and differences to I2C ;-)
<jernej>
DDC is actually more or less I2C
<jernej>
which is used to read EDID
<apritzel>
ah, yes, got confused over those TLAs
<apritzel>
CEC in software .. tricky> because of realtime constraints?
<jernej>
yes, you need stable timer
<apritzel>
you could do that in the management controller, ah wait ... ;-)
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<jernej>
I guess high speed timer or just timer peripherals can be used for such source
<apritzel>
smaeul: thanks for the heads up with the NMI pin, I was just about the check for that "NMI interrupt controller"
<apritzel>
smaeul: I guess I can just skip that
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<jernej>
32k clock output is multiplexed on gpio
<jernej>
I think this is the first time
<apritzel>
jernej: yeah, and there is some ominous "PLL lock debug" pin as well ...
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<smaeul>
I think the PLL debug pin has always been there (GPIO PE14 on A64; ball V21 on H6)
<apritzel>
indeed, do we know what it does?
<smaeul>
it's an analog output, so I'm guessing you program DBG_EN and DBG_SEL in PLL_LOCK_CTRL_REG in the CCU, and you get access to the waveform from somewhere inside the PLL