08:14 <cjearls> Hi, I am attempting to use Linux-on-LiteX-VexRiscv, but I'd like to add my custom core to the board instead of the standard VexRiscv core. I have found that the VexRiscv_Linux.v in pythondata_cpu_vexriscv is the CPU that is being packaged up into the bitstream. Is there a way to rerun synthesis of this core with updated VexRiscv code so I can implement the changes I need?

08:14 <cjearls> I'm using the orangecrab board, in case that is necessary information

08:15 <cjearls> I'm having trouble understanding how the flow from source code to a working design is happening for a few of the pieces of the bitstream and software. I'm working on decoding it by reading the Python scripts, but they bounce around a fair bit between scripts, so I was hoping someone might know what direction I'm looking to go in and have advice on how to more effectively get there

18:29 <scanakci> Hi cjearls, I did not play with vexriscv. Based on my previous experience with another cpu, you should be starting with cpu.py for you your core. https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/cpu/vexriscv/core.py#L260

18:30 <scanakci> For instance, vexriscv fetches the necessary code here from pythondata_cpu_vexriscv folder. I am not sure how Linux-on-Litex-VexRiscv designed, though.

19:16 <cjearls> scanakci: Do you mean core.py? It looks like you're right, I'll take a closer look and see if I can find what I'm looking for. Thanks.

20:40 <scanakci> @cjearls: yeah core.py. welcome