00:02 <Dolu> mithro, that's actualy my plan ^^

00:03 <Dolu> having a single FPU shared between the CPU

00:03 <Dolu> basicaly, the goal is that the addition of the FPU in a multicore system would not hit the area that much to make it a kind of "default" option.

00:04 <Dolu> The main thing is that it would allow to run without penality software that were written with the assumption that float/double are free

00:06 <sorear> there's also a range of FP implementation options

00:06 <Dolu> Typicaly, MPG123 use float by default, also seems like SDL2 realy like using float for audio convertions, making it totaly unusable

00:08 <Dolu> So currently the idea was to have float and double converted in load/store into the FPU native format, which could be anything (ex : less than 32 bits native float to save area but allow software to run smoothly)

00:11 <Dolu> but i don't know so much yet about all the float traps/sneaky stuff XD

00:13 <mithro> Dolu: I'm wondering if an FPU based around "hardware assisted soft float" could be performant...

00:15 <Dolu> mithro: Ahhh so, "microcoding" the FPU ?

00:15 <mithro> Dolu: yeah, kinda I guess

00:23 <Dolu> Seems to me that it could be a good middle ground between FPU and software implementation for performances, but i haven't started any FPU design yet to have a good idea about the area.

09:46 <lf_> is there an example on how to use the udp stream port with the liteeth? i am useing an colorlight 5a-75e.

10:05 <_florent_> lf_: https://github.com/enjoy-digital/liteeth/blob/master/liteeth/frontend/stream.py convert a LiteX stream (valid/ready/data) to / from UDP streams

10:06 <_florent_> lf_: I started refactoring the examples/bench, but haven't added a example for UDP stream yet

10:07 <_florent_> lf_: you can eventually revert LiteEth to commit 5247a2008aca5ae5bfa1dc017701373cf3951d08 to have the example on Versa ECP5 with UDP Loopback

10:08 <lf_> ah thanks will try that

17:09 <roboknight> Now that I've gotten the VexRiscv working on the alchitry cu, and it seems to boot from the flash... I'd like to add a component to Litex.

17:10 <roboknight> An LPC bus. It is all Verilog. I see the CPU examples that use pythondata... but they seem to depend on finding things in CPU.

17:10 <roboknight> Is there a different/better way to add something like this?

17:11 <_florent_> roboknight: Hi, you can integrate Verilog/VHDL sources directly

17:11 <roboknight> Ahh, how do you go about doing that? Because that would work for me as well.

17:12 <_florent_> roboknight: you can find some nice examples in Betrusted: https://github.com/betrusted-io/gateware/tree/master/gateware

17:12 <roboknight> I'll look there. Thanks.

17:12 <_florent_> ex here where a I2C core is integrated: https://github.com/betrusted-io/gateware/blob/master/gateware/i2c/core.py

17:12 <_florent_> this is the verilog instance: https://github.com/betrusted-io/gateware/blob/master/gateware/i2c/core.py#L106-L129

17:13 <_florent_> connected to internal Migen/LiteX signals

17:13 <_florent_> and sources are added here: https://github.com/betrusted-io/gateware/blob/master/gateware/i2c/core.py#L130-L132

17:14 <roboknight> Just saw the I2C core... that looks exactly like what I'd like to do.

17:15 <roboknight> Thanks. That sure makes it significantly easier than trying to make a pythondata module.

17:19 <_florent_> the pythondata modules are here to replace submodules to distribute the different CPUs, for you own project you can just have the Verilog/VHDL files directly in your project

17:27 <roboknight> The only thing I'm confused about is where the platform.add_source is "going"... It shows "deps" "gateware" "gateware" "i2c" in the os.path.join... But the verilog source appears to be in the same path as the core.py.

17:27 <roboknight> So I'd like to work out what I need to do to be able to find the verilog source.

19:17 <chrisps> is building any of the pcie examples supported on windows

19:17 <chrisps> does anyone here have a vcu1525

19:17 <chrisps> im kind of at the end of my rope with this thing

19:18 <chrisps> i set up LITEX_ENV_VIVADO=E:\Xilinx\Vivado\2020.2

19:19 <chrisps> and installed everything in the guide

19:19 <chrisps> https://pastebin.com/sSNawA3N

19:19 <tpb> Title: INFO:SoC: __ _ __ _ __INFO:SoC: / / (_) /____ | |/_/IN - Pastebin.com (at pastebin.com)

20:15 <lf_> mmh i think i break the ethernet on my colorlight. is there any good way to test that?

20:17 <lf_> or it does just not work with the timmings

20:35 <lf_> also i am not 100% sure but this clock rename might not be needed: https://github.com/enjoy-digital/litex/blob/master/litex/soc/integration/soc.py#L1377

20:35 <_florent_> chrisps: can you add vivado binaries to your PATH?

20:38 <_florent_> lf_: if you want to check your hardware and have a revision 7.0 you can find a bitstream here: https://github.com/enjoy-digital/colorlite/issues/5#issuecomment-732107745

20:39 <_florent_> you can try to load it and ping it at 192.168.1.20

20:43 <lf_> _florent_: i have a 75e v7.1 but ethernet might be pin competible. i will test that and if i will have to get another board ready

23:29 <somlo> shorne: ping