<cr1901_modern>
_florent_: I figured out the problem I was seeing. It's relevant to orangecrab but may exist on other boards.
<cr1901_modern>
Basically, the USB clock domain on orangecrab wasn't being reset properly. This means the CDC gray code multiregs between USB and sys would not be updated with valid reset values, and the comparison to detect an empty receive queue from USB would be garbage
<cr1901_modern>
The CPU would always see a high level after reset from the RX interrupt. Since it's edge-triggered, the event never triggered, so the RX queue was never serviced
<cr1901_modern>
eventually, the RX queue fills up, and the USB core dies waiting for the RX queue to drain. Then when you send data from the CPU side, the TX queue fills up b/c the USB core refuses to drain it
<cr1901_modern>
Eventually, the BIOS dies in an infinite loop waiting for the TX queue to drain in a vicious cycle.
<cr1901_modern>
Solution is to make sure the USB clock domain actually resets :)
<cr1901_modern>
(This didn't take me as long as you'd think to figure out. But still probably should've waited to debug this.)
<cr1901_modern>
Hrm, actually... this might not be an ideal solution if you _want_ the USB core to stay attached between resets
<cr1901_modern>
Anyways, we can talk more about what you want to do when you're awake
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<_florent_>
cr1901_modern: thanks for the analysis. On the OrangeCrab it's indeed useful to avoid reseting the USB-ACM with the button (that we are using as a reset), this allow reseting the SoC without reseting the USB-ACM link
<_florent_>
we should be able to fix the issue you saw while keeping this behavior
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<cr1901_modern>
_florent_: I'm not sure how to do this in gateware nicely. One solution is software is to change the BIOS to force fake reads from the UART rxtx register until the rx gray counter pointer matches the USB domain's current value
<cr1901_modern>
But that's not intuitive/requires a nice big comment