<_florent_>
cr1901_modern: not sure about xics, I just know we are using a specific commit of pythondata-cpu-microwatt since things were moving fast in the microwatt repo
<nickoe>
How should I understand that? Is that because four bytes are read for each word read?
<zyp>
sounds like 16 to me
<nickoe>
I don't understand why the awidth is not just 32.
<zyp>
2**4 is 16, and if you've got a 32-bit address accessing a 16-byte word then the lower four bits in the address will be all zeroes, so you can shift it by 4 and only keep the upper 28 bits of the address
<zyp>
I don't know the details of the particular code you're looking at, but I guess something like this is what is going on
<zyp>
if you have a 32-bit wide data bus, it's common to leave out the bottom two address bits
<zyp>
and in this case it sounds like you've got 128-bit wide data
<nickoe>
mm, ok, I guess that makes sense a the RAM is accessed with 128 bit widths for the data?
<nickoe>
= 16 bytes
<zyp>
that's how it sounds to me
<zyp>
I think that's a result of the dram being accessed in bursts
<nickoe>
"bursts" is that a general term used for SDRAM?
<zyp>
I'm not an expert on SDRAM, but as far as I understand it you can't ask a RAM for only one word, it'll give you a burst of 8 words or something,
<nickoe>
How many sysclk cycles does it take to read that from the RAM?
<nickoe>
zyp: ok, that sounds about right
<zyp>
several, it's part of the reason SDRAM has higher latency :)
<zyp>
I mean, I figure bursts are a throughput optimization
<nickoe>
in thi case it is also ddr3
<zyp>
if there's a several cycle delay for the memory to locate the data you asked for, it makes sense to return more than just a single word at a time
<nickoe>
yes
<zyp>
but as far as I'm concerned, the details are not all that interesting unless you're writing the memory controller, I just want to use the memory controller :)
<nickoe>
yeah, my goal is also just to _use_ it and not write it.
<nickoe>
How can I buffer my data such that I can push it out at a sysclk rate?
<zyp>
think in terms of streams
<nickoe>
Well, I do want to attempt to stream out data from the ram. I wanted to read it with LiteDRAMDMAReader and then push it in to an AXI Stream Interface.