_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://freenode.irclog.whitequark.org/litex
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<yootis> Is there an easy way to generate verilog of litescope and the UART interface so I can insert it into a verilog-only design?
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<pftbest> Hello. I have some questions about ethernet in litex
<pftbest> When I add self.add_etherbone(phy, ip, mac) I should be able to ping the board right? because with_icmp is True by default?
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