00:13 <nickoe> Is it possible to simulation teh whole SoC?

04:34 <yfl> hi!

04:34 <sorear> o/

04:35 <yfl> I'm a bit stuck with attaching a 16 bit memory to wishbone.SRAM() anyone has tried that?

04:36 <yfl> mem = Memory(32, depth); sram = wishbone.SRAM(mem); # works

04:36 <yfl> mem = Memory(16, depth); sram = wishbone.SRAM(mem); # doesn't work

04:41 <yfl> ... or is that maybe a stupid thing to do?

08:03 <_florent_> nickoe: Hi, LiteX has been initially developed to create custom FPGA systems for clients. It's still used mostly for that and also maintained/improved by funds providing from this work so the cores components are still at https://github.com/enjoy-digital but https://github.com/litex-hub has been created to ease collaborative projects.

08:04 <_florent_> for the bscan_spi, it's just that the bscan_spi bitstream is creating a bridge between BSCAN (JTAG) and SPI to allow programming the SPI Flash over JTAG.

08:11 <_florent_> nickoe: for the mars_ax3 port, the constraint does not seem correct here: https://github.com/litex-hub/litex-boards/compare/master...nickoe:mars_ax3#diff-b7169b52e0788b6269990fe1432222bb2de2876cf0b39a34ab82514b7e3e60b0R140

08:12 <_florent_> not sure clk10 exists, you should use clk50 that is use as the input of the PLL

08:14 <_florent_> I would also recommend increasing sys_clk_freq, on Artix7 the default configuration on Arty has no trouble reaching 100MHz.

08:17 <_florent_> somlo: I've been able to reproduce https://github.com/enjoy-digital/litex/issues/802 on Nexys4DDR, but haven't been able to have a closer look at it yet, I'll do it soon.

08:19 <_florent_> somlo: otherwise for the SDCard issue under Linux, we could create an issue for that (eventually in linux-on-litex-rocket if easier for you), with steps to reproduce and eventual Litescope debug code, this can allow us to converge faster.

13:56 <somlo> _florent_: thanks. I'll run a few more experiments with sdcard, then write it all down in an issue, so we have something concrete to work from...

14:55 <mikeK_de10nano> I would like to do a PR, But which repository do I submit it too? "Litex" proper? I don;t see it?

14:58 <geertu> mikeK_de10nano: didn't "git push" (to github) suggest you to do a PR? Just follow the printed URL?

15:00 <mikeK_de10nano> yup.. working on it. working on PR, Sorry i am not a Software guy. OK I see the difference, Which Repo is which? I see both "Litex-hub" and the repo "enjoy-digital"  So litex Proper is there..  I am a bit confused by the two repo's... looking at it 10000 feet..  Thanks.

15:01 <mikeK_de10nano> I send the PR to enjoy-digital -> litex.. I think.

15:04 <Melkhior> @somlo _florent_ On the sdcard, I might have a line of what is going wrong in my case with rocket in the BIOS: could it be the memory bandwidth is too low compared to the sdcard DMA engine ?

15:04 <Melkhior> For unrelated reason I had to try a slower VexRiscv ('P' has *lot* of instructions, timing is a problem), and at 60 MHz I had the same failure mode in the BIOS as I have with a 60 MHz Rocket ... but that also means the memory is running @240 MHz instead of 320-400 MHz when VecRiscv is running at 80-00 MHz ... the sdram test shows a lowered memory

15:04 <Melkhior> bandwidth, about 19 MB/s vs. 23+ MB/s for 80+ MHz using VexRiscV...

17:42 <_florent_> Melkhior: the DMA engine should handle backpressure when the memory bandwidth is too slow, but doing some explicit tests with an artificially reduced bandwidth could be useful to be sure all cases are covered

21:16 <mikeK_de10nano> :q!

21:16 <mikeK_de10nano> oops

21:26 <somlo> vi user, nice :D

21:32 <mikeK_de10nano> :)   tanks..

21:36 <nickoe> _florent_: ok, thank you for the explanation. And about my board.. I am not sure how that clk10 got there, but I will try to adjust it for clk50 as a start. thank you for replying.

21:37 <nickoe> I am not really sure what that do_finalize thing even does.

21:40 <nickoe> Still same failure. I did use 5MHz on the litex-buildenv project as well .. where I did see the memtest pass.

22:42 <nickoe> _florent_: My board has a 50MHz clock as a base clock, but I guess I can double it somehow.

22:52 <nickoe> _florent_: one difference is that I don't derive from the SoCSDRAM as https://github.com/nickoe/litex-buildenv/blob/mars_ax3/targets/mars_ax3/base.py#L34

23:00 <nickoe> I have no idea how to debug this :/

23:10 <nickoe> hmm

23:16 <nickoe> _florent_: Ok, it does seem to help to use the 100MHz sysclock for some reason. https://github.com/litex-hub/litex-boards/commit/edb8cb188c61d45596d34c6a9266889df65e01c4