00:00
tpb has quit [Remote host closed the connection]
00:00
tpb has joined #litex
00:09
lf_ has quit [Ping timeout: 260 seconds]
00:09
lf has joined #litex
01:41
_whitelogger has joined #litex
01:48
kgugala has quit [Ping timeout: 276 seconds]
03:22
kgugala has joined #litex
03:24
Degi_ has joined #litex
03:27
Degi has quit [Ping timeout: 272 seconds]
03:27
Degi_ is now known as Degi
03:31
lkcl has quit [Ping timeout: 246 seconds]
03:45
lkcl has joined #litex
04:29
_whitelogger has joined #litex
06:13
proteusguy has joined #litex
06:33
TMM has joined #litex
06:43
Bertl_oO is now known as Bertl_zZ
07:02
dayjaby has quit [Ping timeout: 240 seconds]
08:09
indy_ is now known as indy
09:59
lkcl has quit [Ping timeout: 265 seconds]
10:12
lkcl has joined #litex
10:27
futarisIRCcloud has quit [Quit: Connection closed for inactivity]
11:25
tecneecs has joined #litex
12:22
futarisIRCcloud has joined #litex
12:24
mikeK_de1soc has joined #litex
13:33
tecneecs has quit [Quit: Connection closed for inactivity]
14:14
Bertl_zZ is now known as Bertl
14:25
mikeK_de1soc has quit [Quit: Connection closed]
14:36
jimbzy_ is now known as jimbzy
14:41
futarisIRCcloud has quit [Quit: Connection closed for inactivity]
15:57
futarisIRCcloud has joined #litex
17:41
kgugala has quit [Read error: Connection reset by peer]
17:41
kgugala has joined #litex
18:30
dayjaby has joined #litex
18:51
andrewb1999 has joined #litex
19:36
TMM has joined #litex
20:06
lkcl has quit [Ping timeout: 240 seconds]
20:09
andrewb1999 has quit [Quit: Konversation terminated!]
20:17
<
dayjaby >
Nice, feel free to create a pull request with that :)
20:19
lkcl has joined #litex
20:28
Bertl is now known as Bertl_oO
20:53
Guest79985 has joined #litex
20:55
JJJollyjim has joined #litex
21:29
<
nickoe >
dayjaby: Well, I have not idea if that hides other problems or not
22:04
<
nickoe >
I don't get this, in my vcd output file from my simlation I can't get the leds , but a friend of mine do get it! :O
22:04
<
nickoe >
to to the targets dir
22:04
<
nickoe >
generate a demo.bin
22:05
<
nickoe >
./mars_ax3_sim_litex.py --with-sdram --sdram-init=demo.bin --with-analyzer --trace
23:09
<
nickoe >
somlo: What does that mean?
23:10
<
nickoe >
I thought the registers were always 32 bit for a 32 bit riscv?
23:12
<
somlo >
nickoe: in LiteX, "CSR" is slang for an MMIO device register (not to be confused with risc-v CSRs, which are a rather different thing altogether)
23:13
<
nickoe >
but meh, I am just stuck with my simulation here
23:18
<
nickoe >
I a not sure I have the brainwidth to consume that right now
23:19
<
somlo >
I sympathize with that -- it's been a LOOONG February, glad it's almost over :)
23:33
dayjaby has quit [Ping timeout: 240 seconds]