_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://freenode.irclog.whitequark.org/litex
tpb has quit [Remote host closed the connection]
tpb has joined #litex
lf_ has quit [Ping timeout: 260 seconds]
lf has joined #litex
_whitelogger has joined #litex
kgugala has quit [Ping timeout: 276 seconds]
kgugala has joined #litex
Degi_ has joined #litex
Degi has quit [Ping timeout: 272 seconds]
Degi_ is now known as Degi
lkcl has quit [Ping timeout: 246 seconds]
lkcl has joined #litex
_whitelogger has joined #litex
proteusguy has joined #litex
TMM has quit [Quit: https://quassel-irc.org - Chat comfortably. Anywhere.]
TMM has joined #litex
Bertl_oO is now known as Bertl_zZ
dayjaby has quit [Ping timeout: 240 seconds]
indy_ is now known as indy
lkcl has quit [Ping timeout: 265 seconds]
lkcl has joined #litex
futarisIRCcloud has quit [Quit: Connection closed for inactivity]
tecneecs has joined #litex
futarisIRCcloud has joined #litex
mikeK_de1soc has joined #litex
tecneecs has quit [Quit: Connection closed for inactivity]
Bertl_zZ is now known as Bertl
mikeK_de1soc has quit [Quit: Connection closed]
jimbzy_ is now known as jimbzy
futarisIRCcloud has quit [Quit: Connection closed for inactivity]
futarisIRCcloud has joined #litex
kgugala has quit [Read error: Connection reset by peer]
kgugala has joined #litex
dayjaby has joined #litex
andrewb1999 has joined #litex
TMM has quit [Quit: https://quassel-irc.org - Chat comfortably. Anywhere.]
TMM has joined #litex
lkcl has quit [Ping timeout: 240 seconds]
andrewb1999 has quit [Quit: Konversation terminated!]
<nickoe> _florent_: Hi. Did you see my comment in https://github.com/enjoy-digital/litex/issues/712#issuecomment-786304560 ?
<dayjaby> Nice, feel free to create a pull request with that :)
lkcl has joined #litex
Bertl is now known as Bertl_oO
Guest79985 has joined #litex
JJJollyjim has joined #litex
<nickoe> dayjaby: Well, I have not idea if that hides other problems or not
<nickoe> I don't get this, in my vcd output file from my simlation I can't get the leds , but a friend of mine do get it! :O
<nickoe> to to the targets dir
<nickoe> generate a demo.bin
<nickoe> ./mars_ax3_sim_litex.py --with-sdram --sdram-init=demo.bin --with-analyzer --trace
<nickoe> even though I have read through https://github.com/enjoy-digital/litex/wiki/Use-LiteScope-To-Debug-A-SoC a couple of times. I still struggle to understand what I can give to the analyzer_signals
<somlo> 32-bit CSR data width support has landed upstream -- thanks again shorne_ ! (https://github.com/torvalds/linux/commit/a3905af5be36b9aa9f17657a02eeb2a08e939c13)
<nickoe> somlo: What does that mean?
<nickoe> I thought the registers were always 32 bit for a 32 bit riscv?
<somlo> nickoe: in LiteX, "CSR" is slang for an MMIO device register (not to be confused with risc-v CSRs, which are a rather different thing altogether)
<nickoe> ah, ok
<nickoe> but meh, I am just stuck with my simulation here
<somlo> nickoe: https://github.com/enjoy-digital/litex/wiki/CSR-Bus for the gory details :)
<nickoe> I a not sure I have the brainwidth to consume that right now
<somlo> I sympathize with that -- it's been a LOOONG February, glad it's almost over :)
dayjaby has quit [Ping timeout: 240 seconds]