_florent_ changed the topic of #litex to: LiteX FPGA SoC builder and Cores / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://freenode.irclog.whitequark.org/litex
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<Melkhior> somlo _florent_ Is HW design some sort of dark art ?:-)  Rocket is willing to load the boot.bin from the micro-sd card ... in SPI mode, as suggested by somlo.
<Melkhior> So theoretically, SPI mode can work ; why can't it work for VexRiscV or my design, your guess is as good (or waaaaaay better if I'm honest) than mine :-)
<Melkhior> ... well back to normal: fixed the boot.bin to have a proper dts (with a SPI sdcard instead of SD-mode), regenerated the bitstream ... and SPI mode now fail as well.
<Melkhior> Guess I'll fall back to serialboot
<Melkhior> Removed the sdcard from the DTS, serialboot'ed:
<Melkhior> # cat /proc/cpuinfo
<Melkhior> processor : 0
<Melkhior> hart : 0
<Melkhior> isa : rv64imafdc
<Melkhior> mmu : sv39
<Melkhior> uarch : sifive,rocket0
<Melkhior> Apparently, the sdcard is the 'root' of all evil ;-)
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<somlo> Melkhior: in spi-mode, the sdcard only uses CSR/MMIO to transfer data -- while "native" litesdcard uses DMA. So the data takes very different paths between RAM and the actual microSD card
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<somlo> then there's the somewhat less likely issue of electrical power. e.g., I have a trellisboard which also works fine with spi-mode sdcard, but will reset/crash the fpga when the physical card is inserted when using native mode -- *unless* I use an external power supply, which allows it to work fine...
<Melkhior> @somlo so tw problems - one is SD-mode w/ rocket where the DMA fails, the other is that for some reason SPI-mode is essentially not working for me ? (it does worke very occasionnaly for reasons unknown...)
<Melkhior> Could be power, but with LiteX I have an external power supply rated 5V/3A (the SBus is limited to 5V/2A). Could be not enough capacitance/decoupling/...  ? I didn't really think about that bit when doing the board...
<somlo> pcb design and power are waaay outside my comfort zone :)
<Melkhior> mine too :-)
<Melkhior> Also I suppose sd-mode, being faster with more pins, is more power-hungry than SPI (as in your experience with the trellisboard)... and SD-mode is quite reliable read-only to load the kernel + rootfs with linux-on-litex-vexriscv ; it works even with my dual-core SoC with all the extra instructions and bigger cache (got the space in the FPGA, might
<Melkhior> as well use it:-)  ).
<Melkhior> However, Linux doesn't see the sdcard at all, don't know why - it's in /proc/device-tree
<Melkhior> I'm guessing my kernel from buildroot is too old and doesn't have a driver ?
<Melkhior> But newer buildroot don't compile, I'm stuck with 88a268354d
<somlo> I was going to say, depends on the kernel. I'd suggest trying the "litex-rebase" branch of https://github.com/litex-hub/linux
<somlo> also not familiar with buildroot -- I use a raw busybox-based initramfs.cpio for rocket (my current goal is to get things working at all, doing useful stuff with it can wait for later ;)
<Melkhior> Could try that yes, keep the rootfs and only rebuild a newer kernel. Worth a shot...
<Melkhior> Yes, I saw that - your instructions were quite nice, I got a boot.bin that works (via serialboot only;-)  ) fine with Rocket using them
<Melkhior> buildroot had a bit more stuff, which is useful when your SoC has no ethernet and no working mass storage and the only interface to the outside world is the serial console :-)
<geertu> Melkhior: Does https://github.com/geertu/linux/tree/litex-v5.11 work any better?
<geertu> I use the rootfs and opensbi from the prebuilts, but my own kernel
<somlo> shorne: ping
<somlo> brb
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<Melkhior> @geertu I'll try ASAP
<Melkhior> @geertu Was able to compile to a 'good' image: the kernel loads fine; however I get a hang when accessing the sdcard it seems:
<Melkhior> [ 1.387471] printk: bootconsole [sbi0] disabled
<Melkhior> [ 1.387471] printk: bootconsole [sbi0] disabled
<Melkhior> [ 1.407928] libphy: Fixed MDIO Bus: probed
<Melkhior> [ 1.410771] i2c /dev entries driver
<Melkhior> [ 1.416094] litex-mmc f0005000.mmc: invalid resource
<Melkhior> [ 1.416925] MAP_RESOURCE 2 failed
<Melkhior> (and yet both the kernel and rootfs were loaded from said sdcard!)
<somlo> that's the devm_ioremap_resource call on the sdreader MMIO range failing
<somlo> Melkhior: the bios (loading kernel and rootfs) are a different code base; once the kernel starts booting, it won't use the bios, but rather its own built-in driver to talk to the hardware
<somlo> low-hanging-fruit: typo in the DT node for the sdcard (wrong address for the third entry, the one specific to the sdreader)?
<Melkhior> OK ; btw @somlo I also tried the branch you suggested, but I must have messed up the configuration - I got a > 22 MiB image that wouldn't boot. @geertu branch has a default vexriscv config that worked for me
<Melkhior> DTS is
<Melkhior>                 mmc@f0005800 {
<Melkhior>                         compatible = "litex,mmc";
<Melkhior>                         bus-width = <0x4>;
<Melkhior>                         reg = <0xf0005000 0x100 0xf0005800 0x100>;
<Melkhior>                         status = "okay";
<Melkhior>                 };
<somlo> the litex_rebase branch needs a vexriscv defconfig :)
<somlo> you have too few entries in reg
<somlo> you need four (address, size) pairs
<Melkhior> should come out of json2dts.py ...
<Melkhior> I _think_
<Melkhior> Source file should be ./build/sbustoztex/sbustoztex.dts from linux-on-litex-vexriscv, says:
<Melkhior>                 mmc0: mmc@f0005800 {
<Melkhior>                         compatible = "litex,mmc";
<Melkhior>                         bus-width = <4>;
<Melkhior>                         reg = <
<Melkhior>                                 0xf0005000 0x100
<Melkhior>                                 0xf0005800 0x100
<Melkhior>                         >;
<Melkhior>                         status = "okay";
<Melkhior>                 };
<Melkhior> only two as well
<geertu> Melkhior: To fix the too large kernel image, you need https://github.com/geertu/linux/commit/d7894d2d078e5e255fa2e0e8bd3739079a854b39
<somlo> technically, json2dts *should* take care of it, but I haven't adapted it to deal with rocket yet, so I'm not super familiar with it
<Melkhior> @geertu OK thanks; though your branch works for me I might stick with that :-)
<geertu> Melkhior: I have
<geertu> mmc0: mmc@f0004800 {
<geertu> reg = <
<geertu> compatible = "litex,mmc";
<geertu> 0xf0004800 0x100
<geertu> 0xf0005000 0x100
<somlo> the four entries in reg <> should correspond to your csr.csv
<geertu> 0xf0005800 0x100
<geertu> 0xf0006000 0x100>;
<geertu> bus-width = <0x04>;
<Melkhior> @somlo this is with VexRiscV ATM, as it works in the BIOS
<geertu> status = "okay";
<geertu> };
<geertu> also with linux-on-litex-vexriscv?
<somlo> Melkhior: yes, understood. But since it's the same driver in linux, it'll need similar magic in DTS :)
<Melkhior> :-)
<somlo> I was going to say: in csr.csv, you should have sdphy, sdcore, sdblock2mem, sdmem2block
<Melkhior> magic is the word...
<somlo> "csr_base" entries
<somlo> those are your start addresses for each of the four pairs in "reg"
<somlo> use 0x100 for the extent of each pair as that should be "close enough"
<somlo> your json2dts might be out of date or buggy, but as mentioned, I haven't dealt with it yet, so I don't know for sure
<Melkhior> OK will fix that and try again
<Melkhior> (I don't seem to have a csr.csv, but I have a csr.json with the entries in decimal, close enough I guess:-)  )
<Melkhior> mmm, goes further but then infinite loop in the kernel:
<Melkhior> [ 2.697537] litex-mmc f0005000.mmc: Requested clk_freq=0: set to 0 via div=256
<Melkhior> [ 3.745523] litex-mmc f0005000.mmc: Requested clk_freq=12500000: set to 0 via div=2
<Melkhior> [ 4.973482] litex-mmc f0005000.mmc: Requested clk_freq=0: set to 0 via div=256
<Melkhior> [ 6.017523] litex-mmc f0005000.mmc: Requested clk_freq=12500000: set to 0 via div=2
<Melkhior> [ 7.245492] litex-mmc f0005000.mmc: Requested clk_freq=0: set to 0 via div=256
<Melkhior> [ 8.289514] litex-mmc f0005000.mmc: Requested clk_freq=12500000: set to 0 via div=2
<Melkhior> [ 9.517482] litex-mmc f0005000.mmc: Requested clk_freq=0: set to 0 via div=256
<Melkhior> [ 10.561525] litex-mmc f0005000.mmc: Requested clk_freq=12500000: set to 0 via div=2
<Melkhior> [ 11.789480] litex-mmc f0005000.mmc: Requested clk_freq=0: set to 0 via div=256
<Melkhior> [ 12.833513] litex-mmc f0005000.mmc: Requested clk_freq=12500000: set to 0 via div=2
<Melkhior> (repeat ad nauseam)
<Melkhior> in the DTS, what should be the address of the 'mmc' ?
<Melkhior> I have mmc0: mmc@f0005800
<geertu> Melkhior: replace the dev_info() call by dev_dbg()
<geertu> Melkhior: the address depends on what you have configured inyour SoC
<Melkhior> that was the last block of registers, but geertu's DTS uses 4800 (the first block)
<Melkhior> now 5800 is in the middle for me ...
<Melkhior> should it be the first block ?
<Melkhior> that would be f0005000 whic his what the kernel reports
<somlo> Melkhior: when you built the bitstream, did you get/keep the csr.csv file that was generated during the build?
<somlo> it should contain the authoritative addresses that need to be placed in DT specific to your "hardware"
<somlo> look for a line (in csr.csv) starting with "csr_base,sdphy"
<Melkhior> I have a csr.json instead, does it not have all the information ?
<somlo> should have it, although maybe in a slightly different format ?
<somlo> search for "sdphy", "sdcore", sdblock2mem", and "sdmem2block" in your json file
<Melkhior>     "csr_bases": {
<Melkhior> (...)
<Melkhior>        "sdphy": 4026552320,
<Melkhior> that's F0005000
<Melkhior> I fixed the DTS I think, that's how I get the kernel's infinite loop
<Melkhior> I have all four registers, with the same relative offset than Geert's (just a different base)
<somlo> what is the "clock-frequency" value for your CPU (also in DTS)?
<somlo> it's used to compute the divider for clocking the sdcard
<somlo> and it seems that's not going over too well in your environment
<Melkhior> 100 MHz
<somlo> so `clock-frequency = <100000000>;` then ?
<Melkhior> yes
<Melkhior> ... in JSON: 500
<Melkhior> ... in JSON: "config_clock_frequency": 100000000,
<somlo> the line that says "set to 0 via div=2" concerns me a bit
<Melkhior> @geertu with 'dev_dbg' instead of 'dev_info' I get no output ?!?
<Melkhior> @somlo yes seems the code sees host->freq at 0 ...
<Melkhior> I added 'host->freq = 100000000;' in the function, but it doesn't help much:
<Melkhior> [ 2.701396] litex-mmc f0005000.mmc: Requested clk_freq=0: set to 390625 via div=256
<Melkhior> [ 3.745428] litex-mmc f0005000.mmc: Requested clk_freq=12500000: set to 12500000 via di
<Melkhior> v=8
<Melkhior> [ 4.973389] litex-mmc f0005000.mmc: Requested clk_freq=0: set to 390625 via div=256
<Melkhior> [ 6.017425] litex-mmc f0005000.mmc: Requested clk_freq=12500000: set to 12500000 via di
<Melkhior> v=8
<Melkhior> [ 7.245391] litex-mmc f0005000.mmc: Requested clk_freq=0: set to 390625 via div=256
<Melkhior> [ 8.289433] litex-mmc f0005000.mmc: Requested clk_freq=12500000: set to 12500000 via di
<Melkhior> v=8
<Melkhior> (the 'set to XXX' value is 'host->freq / div', so I guess host->freq is 0)
<somlo> Melkhior: I was going to suggest https://pastebin.com/rM6YtKqp but you already did something similar
<Melkhior> mmm the "config_clock_frequency": 100000000," in the JSON doesn't make it all the way to the DTS:
<tpb> Title: diff --git a/drivers/mmc/host/litex_mmc.c b/drivers/mmc/host/litex_mmc.cindex - Pastebin.com (at pastebin.com)
<Melkhior>                 cpu@0 {
<Melkhior>                         clock-frequency = <0x0>;
<somlo> yeah, json2dts again -- maybe hard-code it directly in the dts...
<Melkhior> just did :-)
<somlo> there's something weird about how json2dts seems to not work for you -- I haven't used it, but if it's *this* broken (for linux-on-litex-vexriscv) someone would have noticed, I think. So I wonder where that breakage occurs for you, figuring that out might help fix a bunch of things...
<Melkhior> I'm running a slightly older version from late last october, didn't update everything for fear of breaking something - except for the sdcard (which may still be my HW!) everything works beautifully
<Melkhior> with fixed DTS and unpatched kernel, I also get the 'infinite loop' with the proper divider (8 for 12500000)
<Melkhior> This is SMP as well...
<Melkhior> (OTOH, the 'rocket' tests are with all-new (from yesterday) repositories)
<geertu> Melkhior: Things have changed since last Oct, both on the gateware as Linux driver side
<geertu> So you need to use a recent LiteX, linux-on-litex-vexriscv, and kernel
<Melkhior> Ilitesdcard I _did_ update
<Melkhior> but everything else might be older :-(
<Melkhior> OK
<Melkhior> I will need to restart in a new environment I guess, to have a clean LIteX setup
<Melkhior> might take a while :-(
<Melkhior> Thanks a lot for all the help everyone :-)
<somlo> Melkhior: I have a morning routine of "git pull" for all repos I don't hack on, and fetch-upstream + rebase for everything where I do have current ongoing changes
<somlo> it's a bit of a treadmill, but better to have the latest and greatest, since things do tend to move at a pretty brisk pace :)
<somlo> (even on days I otherwise have no time to play with LiteX, just to make sure I get to complain in a timely way about anything that affects me negatively :)
<Melkhior> ... my main desktop is still on Debian 9 as it works-for-me:-)  My mac laptop is from 2009. And - that FPGA board was bought for https://github.com/rdolbeau/SBusFPGA ; I'm still playing with 25+ years old SPARCstation...
<Melkhior> "latest and greatest" is *not* my middle name :-)
<Melkhior> I guess for LiteX i should learn to update more :-)
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<somlo> _florent_: I built rocket/litex for nexys4ddr with the jtagbone analyzer: https://pastebin.com/72Jdniu8
<tpb> Title: diff --git a/litex_boards/targets/nexys4ddr.py b/litex_boards/targets/nexys4ddr. - Pastebin.com (at pastebin.com)
<_florent_> somlo: not sure I tested jtagbone with the analyzer yet, I was planning to test it later this week
<_florent_> so if you have issues, please report them :)
<somlo> but my old litescope_cli command line: `litescope_cli -v basesoc_cpu_mem_axi_aw_payload_addr 0x80000000 -r basesoc_cpu_mem_axi_w_valid`
<somlo> fails with a `AssertionError: Found multiple candidates:` and a bunch of signals in my list
<somlo> running it without any arguments gets me a dump.vcd
<somlo> but I can't use triggers, apparently
<_florent_> somlo: ok, the issue you have should not be related to the change to jtagbone. This happens when checking the .csv with the passed triggers
<somlo> I can no longer build it the old way did `add_uartbone()` get renamed ?
<somlo> sorry, gotta run (take my Mom in for a vaccine), be back in an hour or so
<_florent_> somlo: uartbone should still work with upstream, I'm going to check
<_florent_> somlo: I'm able to build arty when adding self.add_uartbone(name="serial") to the SoC and doing ./arty.py --uart-name=crossover
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<Zguig> Hi guys, I did something that works to unable flashing the FPGA gateware for: linux virtex project / ecpix5 board (should be compatible with all boards having the flash function working). Could somebody have a look to the issue I have openned to check if I can commit my implementation? https://github.com/litex-hub/linux-on-litex-vexriscv/issues/189
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<_florent_> Hi Zguig, thanks for looking at that, sorry I saw your issue but haven't been able to answer before, just did
<Zguig> Hi _florent_, thanks for your reply, I will have a look to the  https://github.com/quartiq/bscan_spi_bitstreams/blob/master/lattice_bscan_spi.py that is required by OpenOCD to flash if I understood well the story
<Zguig> I did the "easy" way :)
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<_florent_> Zguig: if this is too complicated, we could use an alternative, that would be nice to evaluate ECPProg: https://github.com/gregdavill/ecpprog and ECPDap: https://github.com/adamgreig/ecpdap
<Zguig> It seems not so easy to pass through OpenOCD for this. What don't you like in OpenFPGALoader ? It can do load and flash
<Zguig> In fact it is the official tool from the manufacturer of this board http://docs.lambdaconcept.com/ecpix-5/features/debug.html
<tpb> Title: Debug ECPIX-5 Documentation documentation (at docs.lambdaconcept.com)
<Zguig> What I see nice with this project is the number of FPGA supported
<Zguig> From what I saw in the boards, only few have flash implemented, based on custom routines
<_florent_> Zguig: I have a preference for OpenOCD because that's also what we are using for Xilinx FPGAs
<_florent_> but if using OpenFPGALoader makes flashing a lot easier on ECP5, we could use that
<Zguig> And how did you manage to get the proxy gateware for xilinx?
<_florent_> these are pre-generated
<_florent_> but I was also able to generate them from Migen IIRC
<Zguig> From xilinx tools?
<_florent_> generate with Migen with the Xilinx tools yes
<_florent_> generated
<_florent_> sorry I have to go
<Zguig> OK, thanks! I try to check if I can go further with OpenOCD
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<somlo> _florent_: fwiw, jtagbone and litescope work -- it's that the soc was internally renamed from "basesoc" to just "soc", so the names of the signals I was passing into the client were wrong
<somlo> so I think everything is fine from my perspective -- I can keep the console on the "standard" uart and do debugging/litescope over jtag, which is the intuitive thing to do -- thanks for implementing it, and sorry for the false alarm
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<_florent_> somlo: thanks for the feedback, nice to know it's working correctly. We should really get rid of this renaming, I'll try to look at it soon (https://github.com/enjoy-digital/litex/issues/667)
<somlo> _florent_: litescope is awesome, and I love that I know how to use it now (thanks again for that, btw). But I just came to realize I actually need to understand the LiteSDCard (and DMA) FSMs, to even stand a chance of figuring out why they're misbehaving (and only under Linux, not in the bios)...
<somlo> so it looks like I have to go down a layer of abstraction and learn yet another new thing :D
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