09:06 <Melkhior> Hello all; I have a question about litex & sdcard - are you supposed to be able to see and mount an sdcard if you've booted from serial ? Or is it only to load the kernel & rootfs to memory ?

09:06 <Melkhior> I have a piece of hardware I designed and I can't get the sdcard to work for me from my own gateware (unrelated to LiteX), but I can 'sdcard_detect', 'sdcard_init' and 'sdcard_read' in the LiteX BIOS...

09:06 <Melkhior> I wanted to check the HW more thoroughly using it from Linux-on-VexRiscV, but  I don't see the sdcard in 'dmesg' or in /dev.

09:06 <Melkhior> Thanks for any help :-)

10:54 <_florent_> Hi Melkhior, the SDCard can be used to load images with the BIOS but can also be used from Linux (even if Linux is booted from serial if the SDCard is declared in the .dts).

10:55 <_florent_> But the SDCard support with Linux-on-LiteX-VexRiscv still need to be finished: https://github.com/litex-hub/linux-on-litex-vexriscv/issues/171

10:56 <Melkhior> _florent_ thanks. It's not in my DTS so I guess PIBKAC :-)

10:57 <_florent_> The current status with Linux-on-LiteX-VexRiscv is: with the BIOS: both SPI and SD mode are working. with Linux: SPI mode is working, SD mode still requires somes tests/fixes.

10:57 <Melkhior> I forgot to change the DTB in my 'boot directory' when I added my expansion board, silly me...

10:58 <_florent_> but SD mode is working in Linux with Rocket CPU, so it's probably not a big issue, but still need to be looked at :)

11:00 <Melkhior> BTW - does the sdcard code requires 'wishbone' or does it have a lower-level interface ?

11:00 <Melkhior> Also - I'm trying to add a micro-sd card slot to a 26 years old SPARCstation 20 so the performance of the SD interface is not the primary concern:-)  (or Linux support, only NetBSD has good support theses days)

11:00 <Melkhior> Thanks for the help!

11:06 <acathla> I'm trying to understand why in uart.py, in RS232PHYTX Module there is this line : self.sink = stream.Endpoint([("data", 8)])

11:06 <acathla> Why is TX a sink?

11:11 <zyp> because a UART transmitter needs data to transmit, the sink is receiving that data

11:22 <acathla> Okay, thanks zyp

12:05 <shorne> somlo: FYI, the changes still look good, I may just merge soon

12:38 <somlo> shorne: sounds good, thanks!

13:24 <Melkhior> _florent_ For some reason even with the right DTB I don't see the sd-card from Linux, but once I put the boot files on the sdcard the BIOS instantly boots from it - and a lot faster than from serial :-)

13:24 <Melkhior> I might have an out-of-date/incompatible kernel and/or litesdcard...

13:24 <Melkhior> anyway it shows that my HW is OK at least for reading, I guess

13:24 <Melkhior> Thanks again

17:55 <_florent_> acathla: sink/source is always relative to your point of view (if you see things from inside a Module or outside). Here for RS232PHYTX we are reasoning from outside where the sink receive the data. That's generally the approach that is used in the cores.

17:57 <_florent_> Melkhior: good for the SDCard, if reads work, writes should also work (that's the same 4-bit bus)

17:58 <acathla> _florent_, but in the module there is no fifo, but an Endpoint, and I don't really understand well the logic here

18:00 <_florent_> acathla: that's True that it would be good to add some comments in this code :)

18:00 <acathla> In every code in LiteX :P

18:01 <_florent_> but basically, it receives the data on the sink. On the sink, 3 signals are used: valid/ready/data

18:01 <_florent_> when valid is set to 1 (by the external Module driving it), we have a TX byte to transmit

18:02 <_florent_> the core can then use the data and transmit it

18:02 <_florent_> and then just ack on ready signal when done

18:02 <_florent_> the external module can then just send the next data

18:02 <_florent_> etc...

18:03 <_florent_> The LiteX's streams are very close to AXI streams

18:03 <acathla> I never used AXI streams...

18:03 <_florent_> https://github.com/enjoy-digital/litex/wiki/Streams

18:04 <acathla> I read it, a lot =)

18:05 <acathla> The problem is that I cannot fill the TX FIFO so that the UART says it's full. A If(uart_txfull_read()) { printf("full\n" } uart_rxtx_write(somechar); in a loop never fills the fifo, even at 12MHz when it's a serial thing

18:05 <_florent_> ah ok, maybe you could look at the AXI specification, it's well written and explains things clearly

18:05 <acathla> _florent_, ok

18:06 <_florent_> for example: https://www.xilinx.com/support/documentation/ip_documentation/ug761_axi_reference_guide.pdf

18:06 <_florent_> you can only look at AXI stream

18:08 <_florent_> for your particular case it could just be that the transmitter consumes the data faster than provided by the CPU

18:09 <acathla> How is it possible when it's a serial transmitted feeded by a parallel CPU?

18:10 <acathla> unless it takes many CPU cycles to write to the FIFO

18:10 <_florent_> observing the valid/ready signals of the transmitter's sink could be useful

18:11 <_florent_> (I'm reasoning with the elements I have from our last discussion: SERV CPU, 8-bit CSR, etc... :))

18:11 <acathla> I tried with a vexriscv, with code in RAM, much faster now

18:11 <_florent_> (but you were also not using a regular RS232 transmitter IIRC)

18:12 <_florent_> ok

18:12 <acathla> right, to transmit with InfraRed

18:13 <_florent_> at least, I think you would have a better visibility by including a LiteScope module or outputing some signals to a scope, this would also be very useful to understand how things are working

18:13 <acathla> Last time I tried the design was too big to fit, but I can try now I removed USB

18:15 <acathla> Or try on a bigger FPGA

18:17 <_florent_> Yes I was going to recommend that

18:18 <_florent_> LiteX greatly simplifies switching from a FPGA device/family to another, so I would really recommend prototyping things on a medium/large FPGA first

20:21 <Finde> quick plug that if any of you have projects related to litex, you might want to add them to librecores.org to help others find them :)