08:37 <joseng> oter I saw that the DRAM FIFOs are based on the LiteDRAMDMAReader, thats why I mentioned you. What did you use as a base address? In the DRAM FIFO, the base address is directly passed to the DMAReader/Writer. Maybe its also my problem. (my interface is 256bit wide). Do I need to divide the base address by the width (in bytes?) of the interface?

15:41 <cr1901_modern> _florent_: (repost) I got hw_cdc_eptri working on Windows. I'm making a PR now.

15:49 <cr1901_modern> https://github.com/litex-hub/valentyusb/pull/1

20:17 <joseng> _florent_ or anyone else, can you explain a little how to use the LiteDRAMFIFO? Tried may things now, diffferent base adresses (0 and 0x40000000), different data width (originally I use 18, then switched to 32), but I always read garbade. The length of data I can read when the valid flag is set, is the length I write into it, so something is workin

20:17 <joseng> g.

20:17 <joseng> To get the ports for the DRAM FIFO I use crossbar = self.sdram.crossbar, read_port1 = crossbar.get_port(mode="read"), write_port1 = crossbar.get_port(mode="write")

20:20 <joseng> self.sdram is from my implementation of "class BaseSoC(SoCSDRAM):"

22:11 <mithro> http://www.rsg.ci.i.u-tokyo.ac.jp/members/shioya/pdfs/Mashimo-FPT%2719.pdf

22:11 <mithro> An Open Source FPGA-Optimized Out-of-Order RISC-V Soft Processor

22:24 <scientes> the reference that is not in the paper: https://github.com/rsd-devel/rsd

22:27 <scientes> i find it strange they are targeting a zync board, when they are not using the Cortex-A9 chip

22:28 <scientes> oh they are using the ARM, running Linux, but it is not clear why

22:34 <zyp> I figure they just targeted the board they had available, zynq boards are popular :)

22:57 <munter> im trying to get started with litex, following the quick start guide, but on the step where I run `lxsim --cpu-type=vexriscv` I run into a few errors, specifically `/litex/litex/build/sim/core/veril.cpp:52:8: error: ‘class VerilatedVcdC’ has no member named ‘set_time_unit’`

22:57 <munter> thanks in advance for any help

22:58 <zyp> sounds like a version incompatibility

22:59 <zyp> which verilator version do you have?

23:00 <munter> `Verilator 3.874 2015-06-06 rev verilator_3_872-20-g0d4305`

23:00 <munter> yea, ill try build from source, didnt realise it was that old

23:00 <munter> thanks

23:02 <zyp> for reference, set_time_unit was added in 3.906 from 2017 :)