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<
tpb>
Title: linux.conf.au 2021 | Presentation: Open Source FPGA Tooling, Our Journey from Resistance to Adoption (at lca2021.linux.org.au)
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geertu>
cr1901_modern: default config, OrangeCrab r0.2
<
geertu>
never saw the SDRAM init issues on mine
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andrewb1999>
Is there a way to easily do clock domain crossing for AXI-lite in liteX?
<
andrewb1999>
I want to connect to an axi-lite module that needs to run slower than the main SoC itself
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