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<st-gourichon-fid>
Hi! i have a strange condition where only on one specific machine, litex_simple would fail with: ModuleNotFoundError: No module named 'litex.boards'
<st-gourichon-fid>
Several machines on Xubuntu 20.04, only this one fails. Even reinstalled the whole OS on a different partition.
<st-gourichon-fid>
litex was installed using exactly the same procedure twice. The procedure installs all dependencies in a virtualenv and is repeatable.
<st-gourichon-fid>
We also reinstalled "from scratch" (inside different directory tree, all components "git clone"d again, and a new python virtualenv) on the machine where things worked, and they still work.
<st-gourichon-fid>
How to diagnose why one machine would "ModuleNotFoundError: No module named 'litex.boards'"?
<_florent_>
st-gourichon-fid: litex.boards no longer exists (since no longer useful with the separate litex_boards repository)
<_florent_>
st-gourichon-fid: it's possible I forgot to replace some imports. I'll double check
<_florent_>
ah, litex_simple is no longer part of LiteX (was a target). I'll see if I revert it or if we just use the one from litex_boards
<cr1901_modern>
For now, litex_term should "just work" on Windows with these changes
<st-gourichon-fid>
Notice: in a checked-out and populated (including submodules) installation of litex, this command yields 41 matches: fgrep litex.boards -rI
<st-gourichon-fid>
Experienced again Yossy failure. YOSYS 0.9+3819 allocates LCs instead of RAM, LC consumption explodes, yosys fails. Fixed by using a commit known to work: git checkout aafaeb66dfd839b8223059884d2741dadc9e2d92
<st-gourichon-fid>
s/Yossy/Yosys/
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<_florent_>
cr1901_modern: I saw your PR, thanks! I'm finishing something and will look at it
<roboknight>
I was trying to find a definitive answer to the question of how to address the wishbone bus in python. Are the upper bits of the bus at the lower end of a python array (i.e. would self.bus.adr[4:] exclude the higher bits) or are they at the upper end of a python array (i.e. self.bus.adr[0:28] exclude the higher bits?). I thought I found an answer
<roboknight>
a while back, but I can't find the answer now.
<roboknight>
And is the freenode.irclog down?
<_florent_>
roboknight: self.bus.adr[:4] will take the 4 lower bits, self.bus.adr[4:] will take the uppers bits starting from bit 4.
<_florent_>
(bit 0 = first bit)
<roboknight>
Thanks. That is what I thought, and I *KNOW* I saw an example somewhere, but I just couldn't find it again.
<roboknight>
So, to be clear, if I said something like: self.bus.adr[:-4] ... this will NOT take the lower 4 bits (i.e. I want to ignore them)...
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<_florent_>
roboknight: to ignore the 4 lowers bits it's: self.bus.adr[4:]
<roboknight>
Oh... so then if I wanted to ignore higher order bits it would be self.bus.adr[:4] ? So self.bus.adr is treated as "little-endian"
<roboknight>
?
<_florent_>
to ignore the 4 MSBs, it's self.bus.adr[:-4]