17:08 <joseng> Does anybody have a working example for the DRAM FIFO? Tried now 3 days without any success to get it to write and read. Searched the internet up and down for all code sniplets which use the DRAM FIFO and DMA classes...

17:44 <oter> joseng happy to package my little DMA experiment and share over this coming weekend. What board are you using?

19:11 <joseng> oter that would be great, thanks. I have the NeTV2

20:29 <_florent_> joseng: sorry, I start having difficulties being very responsive on the support, I indeed encourage collaboration on this as you are doing with oter.

20:30 <_florent_> I'm not sure there is a shared example of use for the DRAM FIFO, but having a look at test_fifo can be useful: https://github.com/enjoy-digital/litedram/blob/master/test/test_fifo.py

20:33 <_florent_> if you want more visibility on the signals, you can also try to use LiteScope to do some captures and share them with us: https://github.com/enjoy-digital/litex/wiki/Use-LiteScope-To-Debug-A-SoC

20:38 <somlo> did anyone try to build LiteX for the genesys2 recently? I'm trying `litex-boards/litex_boards/targets/genesys2.py --sys-clk-freq 50e6 --cpu-type vexriscv --cpu-variant linux --with-ethernet --integrated-rom-size 0x10000 --build` and get a timing constraint failure from vivado

20:38 <somlo> note "vexriscv", so it's not because I'm trying to build it with Rocket :)

20:41 <daveshah> What kind of timing constraint failure?

20:41 <daveshah> I think I last tried it about a year ago

20:46 <_florent_> somlo: I'm going to look at it, it should meet timing easily on the xc7a325t, I think some constraints or false paths are not applied correctly.

20:53 <somlo> daveshah, _florent_: here's the relevant fragment from timing.rpt: https://pastebin.com/5jU9aAKa

20:53 <tpb> Title: Max Delay Paths--------------------------------------------------------------- - Pastebin.com (at pastebin.com)

20:53 <daveshah> Yeah that looks like a cross clock issue, _florent_ is right

20:54 <somlo> way above my paygrade ;)

20:55 <_florent_> somlo: I just generated the design locally, I'm going to have a closer look at the timing issue

20:55 <somlo> awesome, thanks!

20:56 <somlo> I'm ultimately interested in `--cpu-type rocket --cpu-variant linuxq` but hopefully the issue is one and the same...

20:57 <daveshah> It looks like a generic reset CDC issue to me

20:57 <daveshah> Not anything processor specific

20:58 <somlo> daveshah: right, from the vivado timing report perspective (and my limited ability to interpret it)

20:58 <daveshah> I don't think it would necessarily stop the design working either

20:59 <somlo> daveshah: haven't actually tried it, my genesys2 is at the office, and I'd have go through decontamination both ways to get in there, so I thought I'd start with just "pretending" :)

23:05 <_florent_> somlo: https://github.com/litex-hub/litex-boards/commit/1ac1c6857fa576174a63af580ed8d615339f2809