<oter>
yoseng I cut/pasted the relevant bits of a LiteDRAMDMAReader example here: https://pastebin.com/Y6cuUAcJ. The bus width etc. (where not generic) are for the ECPIC-5 Lattice board (sorry, don't have yours). It's super naive, but helped me learn. As _florent_ pointed out, love using Litescope to see what's going on. Trigger the example DMA read sequence via a write to the CRG called "output". Any other trigger (button?) would do too.
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<_florent_>
somlo: nice for Rocket, VexRiscv-SMP is in fact very similar and the CPU itself is also almost its own SoC
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<Bk>
Hi, i have a problem with picorv32.
<Bk>
I load on my fpga the project with interrupt enable
<Bk>
but when an interrupt occours the riscV doesn't enter in a irq function
<Bk>
i loaded the example function with a simple counter inside irq function
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<_florent_>
Hi Bk, we would probably need more info about your use case. The default LiteX/PicoRV32 configuration uses interrupts for the UART and seems to be behaves correctly:
<_florent_>
this will create a SoC with PicoRV32 and execute the demo app on it
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<cr1901_modern>
how do yo send input to the simulator?
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<_florent_>
cr1901_modern: with litex_sim the UART is redirected to the console
<_florent_>
so it's very similar to using the SoC on hardware through a terminal
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<cr1901_modern>
Ahhh that's cool. I might be able to dup my USB bug (see privmsg) then...
<cr1901_modern>
_florent_: ^^
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<ethanhs>
Hi! Very cool project :)
<ethanhs>
Does anyone know if it is possible to buy a Trellisboard, I've been reading through some of the pcie/ethernet boards litex supports and I'm thinking of getting that or an Acorn