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<Zguig>
geertu, regarding to your issue with Can't open input file `litex/pythondata-cpu-vexriscv-smp/pythondata_cpu_vexriscv_smp/verilog/VexRiscvLitexSmpCluster_Cc1_Iw32Is4096Iy1_Dw32Ds4096Dy1_Ood_Wm.v' for reading: No such file or directory
<Zguig>
I got the same, it is really a question about having your litex projects up to date
<Zguig>
just run ./litex_setup.py update
<Zguig>
Make sure there is no conflicts and everything is updated and this will work
<Zguig>
For me as I had done modifications on files, it was not possible to be updated, I had to create a copy of the files I was wanting to keep and do a git reset --hard on the conflicting repos
<Zguig>
this last command is to remove all your modifications (so the need to save them befoire)
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<Melkhior>
geertu I don't have the file in an up-to-date checkout either; what is your CPU config ? I don't see the memory width in the filename ? (e.g. _Ldw128_)
<Melkhior>
mmmm, means you use 'wishbone memory'
<Melkhior>
(Wm), those don't seem to be pregenerated ?
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<Zguig>
Melkhior, for me, I have this file: ls ../pythondata-cpu-vexriscv-smp/pythondata_cpu_vexriscv_smp/verilog/
<Zguig>
Maybe auto generated depending on the board and cpu conf?
<Melkhior>
Presumably, I don't see the Wishbone-memory file in GitHub either, and they don't seem to be generated by generate_default_configs in litex/litex/soc/cores/cpu/vexriscv_smp/core.py