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<geertu>
Anyone else getting this?
<geertu>
Can't open input file `litex/pythondata-cpu-vexriscv-smp/pythondata_cpu_vexriscv_smp/verilog/VexRiscvLitexSmpCluster_Cc1_Iw32Is4096Iy1_Dw32Ds4096Dy1_Ood_Wm.v' for reading: No such file or directory
<geertu>
I do have the updated litex_setup.py that does the submodule update
<geertu>
Doing a manual submodule update doesn't make a difference
<geertu>
_florent_: Building now after reverting dee4331dc39124bc ("make/soc_linux: use Wishbone memory accesses/L2 cache on boards not supporting direct LiteDRAM interface (no DM supoport).")
<geertu>
The result hangs after Liftoff!, though :-(
<geertu>
Not easy to bisect, due to interdependencies among linux-on-litex-vexriscv, litex, litex-boards, ...
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<_florent_>
geertu: have you try doing a git submodule update --init --recursive in pythondata-cpu-vexriscv-smp?
<_florent_>
try/tried
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<geertu>
_florent_: I hadn't tried the --recursive. Just did, and no difference
<geertu>
litex_setup.py had have done the --recursive before anyway